Cell circuit and layout with linear finfet structures

Patent metadata

Field	Value
Publication number	US-9563733-B2
Application number	US-77542910-A
Country	US
Kind code	B2
Filing date	May 6, 2010
Priority date	May 6, 2009
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

First claim

What is claimed is:

1. A cell circuit of a semiconductor device, comprising:
a substrate;
a number of linear-shaped diffusion fins defined to extend over the substrate in a first direction so as to extend parallel to each other, each of the number of linear-shaped diffusion fins defined to project upward from the substrate along their extent in the first direction, wherein the number of linear-shaped diffusion fins are positioned on one or more of a plurality of diffusion tracks that are virtual lines of a diffusion fin virtual grate, wherein the plurality of diffusion tracks extend in the first direction over the substrate, wherein the plurality of diffusion tracks are positioned based on a fixed diffusion track pitch, wherein the fixed diffusion track pitch corresponds to an equal spacing between adjacent side-by-side positioned ones of the plurality of diffusion tracks as measured in a second direction perpendicular to the first direction and parallel to the substrate; and
a number of gate level structures defined to extend in a conformal manner over one or more of the number of linear-shaped diffusion fins, such that portions of each gate level structure that extend over any of the number of linear-shaped diffusion fins extend in the second direction perpendicular to the first direction, wherein portions of each gate level structure that extend over any of the number of linear-shaped diffusion fins form gate electrodes of a corresponding transistor.

2. The cell circuit of a semiconductor device as recited in claim 1 , wherein the first direction corresponds to a width direction of the cell circuit, and wherein the fixed diffusion track pitch is related to a height of the cell circuit, such that a continuity of the fixed diffusion track pitch is maintained across boundaries of the cell circuit to form a global set of equally spaced diffusion tracks across a group of neighboring cell circuits.

3. The cell circuit of a semiconductor device as recited in claim 2 , wherein the height of the cell circuit is an integer multiple of the fixed diffusion track pitch.

4. The cell circuit of a semiconductor device as recited in claim 1 , wherein at least one of the plurality of diffusion tracks is partially filled with linear-shaped diffusion fins.

5. The cell circuit of a semiconductor device as recited in claim 1 , wherein at least one of the plurality of diffusion tracks is completely filled with linear-shaped diffusion fins.

6. The cell circuit of a semiconductor device as recited in claim 1 , wherein at least one of the plurality of diffusion tracks is vacant and does not have a linear-shaped diffusion fin positioned thereon.

7. A cell circuit of a semiconductor device, comprising:
a substrate;
a number of linear-shaped diffusion fins defined to extend over the substrate in a first direction so as to extend parallel to each other, each of the number of linear-shaped diffusion fins defined to project upward from the substrate along their extent in the first direction; and
a number of gate level structures defined to extend in a conformal manner over one or more of the number of linear-shaped diffusion fins, such that portions of each gate level structure that extend over any of the number of linear-shaped diffusion fins extend in a second direction perpendicular to the first direction, wherein the portions of each gate level structure that extend over any of the number of linear-shaped diffusion fins form gate electrodes of a corresponding transistor, wherein the portions of each gate level structure that extend over any of the number of linear-shaped diffusion fins are positioned on one or more of a plurality of gate electrode tracks that are virtual lines of a gate level virtual grate, wherein the plurality of gate electrode tracks extend in the second direction over the substrate, wherein the plurality of gate electrode tracks are positioned based on a fixed gate electrode track pitch, wherein the fixed gate electrode track pitch corresponds to an equal perpendicular spacing between adjacent side-by-side positioned ones of the plurality of gate electrode tracks.

8. The cell circuit of a semiconductor device as recited in claim 7 , wherein the second direction corresponds to a height direction of the cell circuit, and wherein the fixed gate electrode track pitch is related to a width of the cell circuit, such that a continuity of the fixed gate electrode track pitch is maintained across boundaries of the cell circuit to form a global set of equally spaced gate electrode tracks across a group of neighboring cell circuits.

9. The cell circuit of a semiconductor device as recited in claim 8 , wherein the width of the cell circuit is an integer multiple of the fixed gate electrode track pitch.

10. The cell circuit of a semiconductor device as recited in claim 7 , wherein at least one of the plurality of gate electrode tracks is partially filled with gate level structures.

11. The cell circuit of a semiconductor device as recited in claim 7 , wherein at least one of the plurality of gate electrode tracks is completely filled with gate level structures.

12. The cell circuit of a semiconductor device as recited in claim 7 , wherein at least one of the plurality of gate electrode tracks is vacant and does not have a gate level structure positioned thereon.

13. The cell circuit of a semiconductor device as recited in claim 7 , wherein the number of gate level structures are positioned to maximally fill each of the plurality of gate electrode tracks that has at least one of the number of gate level structures positioned thereon, wherein breaks are defined between multiple gate level structures along individual gate electrode tracks as needed for cell circuit functionality.

14. The cell circuit of a semiconductor device as recited in claim 13 , wherein the breaks defined between multiple gate level structures along individual gate electrode tracks are uniform in size through the cell circuit.

15. A cell circuit of a semiconductor device, comprising:
a substrate;
a number of linear-shaped diffusion fins defined to extend over the substrate in a first direction so as to extend parallel to each other, each of the number of linear-shaped diffusion fins defined to project upward from the substrate along their extent in the first direction;
a number of gate level structures defined to extend in a conformal manner over one or more of the number of linear-shaped diffusion fins, such that portions of each gate level structure that extend over any of the number of linear-shaped diffusion fins extend in a second direction perpendicular to the first direction, wherein the portions of each gate level structure that extend over any of the number of linear-shaped diffusion fins form gate electrodes of a corresponding transistor; and
a number of local interconnect structures defined between neighboring gate level structures so as to extend in the second direction parallel to the neighboring gate level structures, wherein the number of local interconnect structures are formed of an electrically conductive material, and wherein the number of local interconnect structures are formed at or below a gate level of the cell circuit.

16. A cell circuit of a semiconductor device, comprising:
a substrate;
a number of linear-shaped diffusion fins defined to extend over the substrate in a first direction so as to extend parallel to each other, each of the number of linear-shaped diffusion fins defined to project upward from the substrate along their extent in the first direction;
a number of gate level structures defined to extend in a conform

Assignees

• Becker Scott T
• Tela Innovations Inc

Inventors

• Becker Scott T

Classifications

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/5072 Primary

  Physics · mapped topic