Flip-flop layout architecture implementation for semiconductor device

Patent metadata

Field	Value
Publication number	US-9324715-B2
Application number	US-201414504075-A
Country	US
Kind code	B2
Filing date	Oct 1, 2014
Priority date	Dec 20, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A semiconductor device includes a substrate including PMOSFET and NMOSFET regions. First and second gate electrodes are provided on the PMOSFET region, and third and fourth gate electrodes are provided on the NMOSFET region. A connection contact is provided to connect the second gate electrode with the third gate electrode, and a connection line is provided on the connection contact to cross the connection contact and connect the first gate electrode to the fourth gate electrode.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a PMOSFET region and an NMOSFET region;
a first and a second gate electrode in the PMOSFET region;
a third and a fourth gate electrode in the NMOSFET region;
a connection contact connecting the second gate electrode and the third gate electrode, wherein the connection contact is electrically connected with upper surfaces of the second and third gate electrodes; and
a connection line connecting the first gate electrode and the fourth gate electrode, the connection line crossing over the connection contact.

2. The semiconductor device of claim 1 , wherein an extending line of the first gate electrode is aligned with the third gate electrode, and an extending line of the second gate electrode is aligned with the fourth gate electrode, when viewed in a plan view.

3. The semiconductor device of claim 1 , further comprising a device isolation layer between the PMOSFET region and the NMOSFET region,
wherein the connection line crosses over the connection contact on the device isolation layer.

4. The semiconductor device of claim 1 , further comprising via-holes between the connection line and the first gate electrode and between the connection line and the fourth gate electrode, respectively.

5. The semiconductor device of claim 1 , further comprising:
a fifth gate electrode extending from the PMOSFET region to the NMOSFET region; and
a gate contact in contact with an upper surface of the fifth gate electrode,
wherein the gate contact comprises a portion crossing a sidewall of the fifth gate electrode, when viewed in a plan view.

6. The semiconductor device of claim 1 , further comprising:
a sixth gate electrode and a seventh gate electrode on the PMOSFET and NMOSFET regions, respectively;
a first skip contact in contact with an upper surface of the sixth gate electrode; and
a second skip contact in contact with an upper surface of the seventh gate electrode,
wherein an extending line of the sixth gate electrode is aligned with the seventh gate electrode, when viewed in a plan view,
the first skip contact is connected in common to source/drain regions provided at both sides, respectively, of the sixth gate electrode, and
the second skip contact is connected in common to source/drain regions provided at both sides, respectively, of the seventh gate electrode.

7. The semiconductor device of claim 6 , wherein the first and second skip contacts are connected to the source/drain regions through connection conductive patterns.

8. The semiconductor device of claim 1 , further comprising:
a fifth gate electrode extending from the PMOSFET region to the NMOSFET region, the fifth gate electrode crossing over the device isolation layer; and
a gate contact in contact with an upper surface of the fifth gate electrode, the gate contact being over the device isolation layer.

9. A semiconductor device comprising a flip-flop circuit, wherein the flip-flop circuit comprises:
first and fourth gate electrodes, which are provided on PMOSFET and NMOSFET regions of the semiconductor device, respectively, and to which a scan enable inversion signal is applied;
second and third gate electrodes, which are provided on the PMOSFET and NMOSFET regions, respectively, and to which a scan enable signal is applied; and
a first cross coupled structure connecting the second gate electrode to the third gate electrode and connecting the first gate electrode to the fourth gate electrode,
wherein the first cross coupled structure comprises:
a first connection contact connecting the first gate electrode to the fourth gate electrode; and
a first connection line connecting the second gate electrode to the third gate electrode and crossing the first connection contact, the first connection line crossing over the first connection contact,
wherein an extending line of the first gate electrode is aligned with the third gate electrode, and an extending line of the second gate electrode is aligned with the fourth gate electrode, when viewed in a plan view.

10. The semiconductor device of claim 9 , further comprising:
a fifth gate electrode extending from the PMOSFET region to the NMOSFET region; and
a gate contact in contact with a top surface of the fifth gate electrode,
wherein the gate contact comprises a portion crossing a sidewall of the fifth gate electrode, when viewed in a plan view.

11. The semiconductor device of claim 10 , wherein the first connection contact and the gate contact are provided at substantially the same level from the substrate.

12. The semiconductor device of claim 10 , further comprising power rails crossing the first to fifth gate electrodes,
wherein the power rails and the first connection line are provided at substantially the same level from the substrate.

13. The semiconductor device of claim 9 , further comprising a second cross coupled structure spaced apart from the first cross coupled structure.

14. The semiconductor device of claim 13 , wherein the second cross coupled structure comprises:
sixth and ninth gate electrodes, which are provided on the PMOSFET and NMOSFET regions, respectively, and to which a clock signal is applied;
seventh and eighth gate electrodes, which are provided on the PMOSFET and NMOSFET regions, respectively, and to which a clock inversion signal is applied;
a second connection contact connecting the sixth gate electrode to the ninth gate electrode; and
a second connection line connecting the seventh gate electrode to the eighth gate electrode and crossing over the second connection contact,
wherein an extending line of the sixth gate electrode is aligned with the eighth gate electrode, and an extending line of the seventh gate electrode is aligned with the ninth gate electrode, when viewed in a plan view.

15. The semiconductor device of claim 9 , further comprising a device isolation layer between the PMOSFET and NMOSFET regions,
wherein the first connection line crosses over the first connection contact on the device isolation layer.

16. A semiconductor device, comprising:
a substrate including a PMOSFET region and an NMOSFET region;
a first and a second gate electrode in the PMOSFET region;
a third and a fourth gate electrode in the NMOSFET region;
a device isolation layer between the PMOSFET and NMOSFET regions,
a connection contact connecting the second gate electrode and the third gate electrode;
a connection line connecting the first gate electrode and the fourth gate electrode, the connection line crossing over the connection contact on the device isolation layer;
a fifth gate electrode extending from the PMOSFET region to the NMOSFET region, the fifth gate electrode crossing over the device isolation layer; and
a gate contact in contact with an upper surface of the fifth gate electrode, the gate contact being over the device isolation layer.

17. The semiconductor device of claim 16 , wherein the gate contact comprises a portion crossing a sidewall of the fifth gate electrode, when viewed in a plan view.

18. The semiconductor device of claim 16 , wherein an extending line of the first gate electrode is aligned with the third gate electrode, and an extending line of the second gate electrode is aligned with the fourth gate electrode, when viewed in a plan view.

19. The semiconductor device of claim 16 , further comprising via-holes between the connection line and the first gate electrode and between the connection line and the fourth gate electrode, respectively.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Azmat Raheel
• Sengupta Rwik
• Park Chulhong
• Chun Kwanyoung

Classifications

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/0172

  Manufacturing their gate conductors · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title