Method for forming metal wiring

Patent metadata

Field	Value
Publication number	US-10249531-B1
Application number	US-201815892536-A
Country	US
Kind code	B1
Filing date	Feb 9, 2018
Priority date	Sep 20, 2017
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A method for forming a metal wiring according to embodiments includes forming a first insulating layer on a substrate; forming a catalyst adsorption layer by bringing a surface of the first insulating layer into contact with a solution containing a compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group; forming a second insulating layer different from the first insulating layer on the catalyst adsorption layer; patterning the second insulating layer to form a mask pattern; etching the first insulating layer by a wet etching method; selectively forming a catalyst layer; and forming a metal layer on the catalyst layer by an electroless plating method.

First claim

What is claimed is:

1. A method for forming a metal wiring, comprising:
forming a first insulating layer on a substrate;
forming a catalyst adsorption layer by bringing a surface of the first insulating layer into contact with a solution containing a compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group;
forming a second insulating layer different from the first insulating layer on the catalyst adsorption layer;
patterning the second insulating layer to form a mask pattern;
etching the first insulating layer by a wet etching method using the mask pattern as a mask;
forming selectively a catalyst layer in a region where the first insulating layer is etched; and
forming a metal layer on the catalyst layer by an electroless plating method.

2. The method for forming a metal wiring according to claim 1 , further comprising: removing the mask pattern after the forming the metal layer.

3. The method for forming a metal wiring according to claim 1 , wherein the compound is a compound represented by the following formula (1), at least one of A, B, and C in the formula (1) is the first functional group, at least one of the A, B, and C is the second functional group, and R 1 , R 2 , and R 3 are optionally present linking groups

4. The method for forming a metal wiring according to claim 1 , wherein the second insulating layer is a resin.

5. The method for forming a metal wiring according to claim 1 , wherein the second insulating layer is a photoresist.

6. The method for forming a metal wiring according to claim 1 , wherein the first insulating layer is an oxide, a nitride, or an oxynitride.

7. The method for forming a metal wiring according to claim 1 , wherein a thickness of the catalyst adsorption layer is 2 nm or less.

8. The method for forming a metal wiring according to claim 1 , wherein a chemical solution used in the wet etching method contains hydrogen fluoride, ammonium fluoride, or phosphoric acid.

9. A method for forming a metal wiring, comprising:
forming a first insulating layer on a first substrate;
forming a catalyst adsorption layer by bringing a surface of the first insulating layer into contact with a solution containing a compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group;
forming a second insulating layer different from the first insulating layer on the catalyst adsorption layer;
patterning the second insulating layer to form a mask pattern;
etching the first insulating layer by a wet etching method using the mask pattern as a mask;
forming selectively a catalyst layer in a region where the first insulating layer is etched;
forming a first metal layer on the catalyst layer by an electroless plating method;
removing the mask pattern after the forming the first metal layer; and
bonding the first substrate and a second substrate to bring the first metal layer and a second metal layer into contact with each other, the second metal layer being formed on the second substrate.

10. The method for forming a metal wiring according to claim 9 , wherein the compound is a compound represented by the following formula (1), at least one of A, B, and C in the formula (1) is the first functional group, at least one of the A, B, and C is the second functional group, and R 1 , R 2 , and R 3 are optionally present linking groups

11. The method for forming a metal wiring according to claim 9 , wherein the second insulating layer is a resin.

12. A method for forming a metal wiring, comprising:
forming a first insulating layer on a first substrate;
forming a first catalyst adsorption layer by bringing a surface of the first insulating layer into contact with a solution containing a first compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group;
forming a second insulating layer different from the first insulating layer on the first catalyst adsorption layer;
patterning the second insulating layer to form a first mask pattern;
etching the first insulating layer by a wet etching method using the first mask pattern as a mask;
forming selectively a first catalyst layer in a region where the first insulating layer is etched;
forming a first metal layer on the first catalyst layer by an electroless plating method;
removing the first mask pattern after the forming the first metal layer;
forming a third insulating layer on a second substrate;
forming a second catalyst adsorption layer by bringing a surface of the third insulating layer into contact with a solution containing a second compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group;
forming a fourth insulating layer different from the third insulating layer on the second catalyst adsorption layer;
patterning the fourth insulating layer to form a second mask pattern;
etching the fourth insulating layer by a wet etching method using the second mask pattern as a mask;
forming selectively a second catalyst layer in a region where the fourth insulating layer is etched;
forming a second metal layer on the second catalyst layer by an electroless plating method;
removing the second mask pattern after the forming the second metal layer; and
bonding the first substrate and the second substrate to bring the first metal layer and the second metal layer into contact with each other.

13. The method for forming a metal wiring according to claim 12 , wherein the first compound and the second compound are compounds represented by the following formula (1), at least one of A, B, and C in the formula (1) is the first functional group, at least one of the A, B, and C is the second functional group, and R 1 , R 2 , and R 3 are optionally present linking groups

14. The method for forming a metal wiring according to claim 12 , wherein the second insulating layer and the fourth insulating layer are resins.

Assignees

• Toshiba Memory Corp

Inventors

• Hieno Atsushi
• Nakanishi Tsutomu
• Tanaka Yusuke
• Yoshimizu Yasuhito
• Happoya Akihiko

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W72/01935

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title