GaN-on-si semiconductor device structures for high current/ high voltage lateral GaN transistors and methods of fabrication thereof

Patent metadata

Field	Value
Publication number	US-10249506-B2
Application number	US-201715712373-A
Country	US
Kind code	B2
Filing date	Sep 22, 2017
Priority date	Mar 3, 2016
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

First claim

The invention claimed is:

1. A wafer scale nitride semiconductor device structure comprising:
a silicon substrate having formed thereon a GaN epi-layer stack for a plurality of GaN die, said plurality of GaN die being arranged as an array with dicing streets therebetween;
each GaN die comprising:
a part of the GaN epi-layer stack, the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a two-dimensional electron gas (2DEG) active layer for a lateral GaN transistor; source, drain and gate electrodes of the lateral GaN transistor being provided on a front-side of the GaN epi-layer stack over an active area of the GaN die, an inactive area of the GaN epi-layer stack surrounding said active area of the GaN die, and an overlying interconnect structure comprising metallization and dielectric layers, the overlying interconnect structure defining respective source, drain and gate connections and contact areas; and

a trench structure formed around a periphery of each GaN die in said inactive area, the trench structure comprising a trench etched through layers of the overlying interconnect structure, through the GaN epi-layer stack, and into a surface region of the silicon substrate to a depth below an interface region between the silicon substrate and the GaN epi-layer stack;
the trench structure further comprising a trench cladding, the trench cladding comprising a metal layer and an overlying dielectric passivation layer, the trench cladding extending over inner sidewalls of the trench and sealing surfaces of layers of the interconnect structure, layers of the GaN epi-layer stack and the interface region between the silicon substrate and the GaN epi-layer stack, the metal layer of the trench cladding contacting the silicon substrate within the trench, and the overlying dielectric passivation layer of the trench cladding sealing surfaces of the metal layer of the trench cladding within the trench.

2. The device structure of claim 1 , wherein the trench structure is laterally spaced from the dicing streets around the periphery of each GaN die.

3. The device structure of claim 1 , wherein the trench structure is laterally spaced from a scribe line of the dicing streets around the periphery of each GaN die.

4. The device structure of claim 1 , wherein the trench structure extends across the dicing streets between adjacent GaN die.

5. The device structure of claim 1 , comprising a passivation layer extending conformally over surfaces of the GaN die and extending into the trench to provide the overlying dielectric passivation layer of the trench cladding.

6. The device structure of claim 1 , wherein the metal layer of the trench cladding is conductive and connects the silicon substrate to a source connection of the lateral GaN transistor.

7. The device structure of claim 1 , wherein said metal layer of the trench cladding comprises part of a conductive metal layer defining said contact areas of the transistor and the overlying dielectric passivation layer comprising at least a first dielectric layer sealing surfaces of said metal layer within the trench, and defining contact openings for said contact areas of the transistor.

8. The device structure of claim 7 , wherein said first dielectric layer comprises silicon dioxide, and a second dielectric layer comprising silicon nitride is formed thereon, sealing surfaces of the underlying first dielectric layer, including edges around contact openings in the first dielectric layer and edges of the first dielectric layer within the trench.

9. The device structure of claim 1 , wherein the GaN die further comprises a seal ring formed over the inactive region of the GaN epi-layer stack and surrounding the lateral GaN transistor, the trench structure being formed in the inactive region between the seal ring and the dicing streets around the periphery of each GaN die.

10. The device structure of claim 9 , wherein the metal layer of the trench cladding is conductive and connects the silicon substrate to a conductive metallization layer of the seal ring.

11. A nitride semiconductor device comprising:
a GaN die comprising:
a silicon substrate and a GaN epi-layer stack formed thereon comprising a GaN/AlGaN hetero-layer
structure defining a two-dimensional electron gas (2DEG) active layer for a lateral GaN transistor; source, drain and gate electrodes being provided on a front-side of the GaN epi-layer stack over an active area of the GaN die, an inactive area of the GaN epi-layer stack surrounding said active area of each GaN die; and an overlying interconnect structure comprising metallization and dielectric layers defining respective source, drain and gate connections and contact areas;

a trench structure formed around a periphery of the GaN die, the trench structure comprising a trench extending through layers of the overlying interconnect structure, through layers of the GaN epi-layer stack, and into a surface region of the silicon substrate to a depth below an interface region between the silicon substrate and the GaN epi-layer stack;
the trench structure further comprising a trench cladding comprising a metal layer and an overlying dielectric passivation layer, the trench cladding extending over inner sidewalls of the trench and sealing exposed surfaces of layers of the overlying interconnect structure, layers of the GaN epi-layer stack and the interface region of the GaN epi-layers and the silicon substrate and contacting the silicon substrate within the trench, the dielectric passivation layer of the trench cladding sealing surfaces of the metal layer of the trench cladding within the trench.

12. The device of claim 11 , wherein the metal layer of the trench cladding is conductive and connects the silicon substrate to a source connection of the transistor.

13. The device of claim 11 , wherein the GaN die further comprises a seal ring formed over the inactive region of the GaN epi-layer stack and surrounding the lateral GaN transistor, the trench structure being formed between the sealing ring and the GaN die edges, and wherein the metal layer of the trench cladding is conductive and connects the silicon substrate to a conductive metallization layer of the seal ring.

14. The device structure of claim 11 , wherein said metal layer of the trench cladding comprises part of a conductive metal layer defining said contact areas of the transistor and a surrounding seal ring, said metal layer defining a first layer of the trench cladding extending over the inner sidewalls of the trench and sealing said exposed surfaces of layers of the interconnect structure, layers of the GaN epi-layer stack and the interface region of the GaN epi-layers and the silicon substrate, and contacting the substrate within the trench, and the overlying passivation layer comprising at least a first dielectric layer sealing surfaces of said metal layer within the trench, and defining contact openings for said contact areas of the transistor.

15. The device structure of claim 14 , wherein said first dielectric layer comprises silicon dioxide, and a second dielectric layer comprising silicon nitride is formed thereon, sealing surfaces of the underlying first dielectric layer, including edges around contact openings in the first dielectric layer and edges of the first dielectric layer within the trench.

16. The device of claim 11 , wherein the trench structure is laterally spaced from edges of the GaN die.

17. The device of claim 11 , wherein the trench structure extends to edges of the GaN die.

18. A method of fabrication of the nitride semiconduc

Assignees

• Gan Systems Inc

Inventors

• Macelwee Thomas
• Klowak Greg P
• Tweddle Howard

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P50/646

  of Group III-V materials · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10W74/141

  the encapsulations being on at least the sidewalls of the semiconductor body · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title