Semiconductor device fabrication method capable of scribing chips with high yield

Patent metadata

Field	Value
Publication number	US-9105706-B2
Application number	US-201313922244-A
Country	US
Kind code	B2
Filing date	Jun 20, 2013
Priority date	Apr 30, 2003
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

A semiconductor device fabrication method includes preparing a semiconductor wafer having a plurality of chip areas formed with semiconductor elements and a scribe area having a dicing area in said scribe area for separating said plurality of chip areas, wherein in said scribe area a groove forming area is defined to surround each chip area at a position outside of the dicing area, disposing a multilayer wiring structure including dummy wirings above said semiconductor wafer, said multilayer wiring structure having interlayer insulating films and wiring layers alternately formed, forming a cover layer including a passivation layer, said cover layer covering said multilayer wiring structure, and forming a groove in each said groove forming area, said groove surrounding each of said plurality of chip areas and extending from a surface of said semiconductor wafer and at least through said passivation layer.

First claim

What is claimed are:

1. A semiconductor device fabrication method comprising:
preparing a semiconductor wafer that includes a chip area formed with semiconductor elements and a scribe area located surrounding the chip area, wherein the scribe area includes a dicing area and a groove forming area between the chip area and the dicing area, the chip area being surrounded by the groove forming area;
disposing a multilayer wiring structure above the semiconductor wafer, the multilayer wiring structure including interlayer insulating films and wiring layers alternately formed, the wiring layers including a wiring pattern and a dummy wiring, wherein the wiring layers include an uppermost wiring layer, a first wiring layer which is located under the uppermost wiring layer, and a second wiring layer which is located under the first wiring layer, the uppermost wiring layer does not include the dummy wiring in the scribe area, the first wiring layer includes the dummy wiring in the scribe area excluding the groove forming area and does not include the dummy wiring in the groove forming area, and the second wiring layer includes the dummy wiring in the scribe area and the groove forming area;
forming a cover layer including a passivation layer, the cover layer covering the multilayer wiring structure; and
forming a groove in the groove forming area at least through the passivation layer, wherein a bottom of the groove is lower than an upper surface of the dummy wiring in the first wiring layer and is higher than an upper surface of the dummy wiring in the second wiring layer.

2. The semiconductor device fabrication method according to claim 1 , wherein the uppermost wiring layer is an aluminum wiring layer.

3. The semiconductor device fabrication method according to claim 2 , wherein the wiring layers other than the uppermost wiring layer are copper wiring layers of damascene structure.

4. The semiconductor device fabrication method according to claim 3 , wherein the interlayer insulating films on the copper wiring layers include a copper diffusion preventive layer and an insulating layer formed on the copper diffusion preventive layer.

5. The semiconductor device fabrication method according to claim 1 , further comprising dicing the semiconductor wafer in the dicing area after forming the groove.

Assignees

• Fujitsu Semiconductor Ltd

Inventors

• Otsuka Satoshi

Classifications

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/9232

  with additional elements interposed between layers · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title