Concurrent read and write operations in a serial flash device

Patent metadata

Field	Value
Publication number	US-2016012891-A1
Application number	US-201514719814-A
Country	US
Kind code	A1
Filing date	May 22, 2015
Priority date	Jul 8, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

A method of controlling an NVM device can include: (i) receiving, by an interface, a write command from a host; (ii) beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of NVM cells arranged in a plurality of array planes; (iii) receiving, by the interface, a read command from the host; (iv) suspending the write operation in response to detection of the read command during execution of the write operation; (v) beginning execution of a read operation on a second array plane in response to the read command; and (vi) resuming the write operation after the read operation has at least partially been executed.

First claim

What is claimed is:

1 . A non-volatile memory (NVM) device, comprising:
a) an interface configured to receive write and read commands from a host; b) a memory array comprising a plurality of NVM cells arranged in a plurality of array planes; and c) a memory controller configured to execute a write operation on a first of the plurality of array planes in response to the write command, and to execute a read operation on a second of the plurality of array planes in response to the read command, wherein the memory controller is configured to suspend the write operation in response to detection of the read command during execution of the write operation, and wherein the memory controller is configured to resume the write operation after the read operation has at least partially been executed.

2 . The NVM device of claim 1 , wherein the read command comprises a plurality of clock cycles added to allow time for the write operation to be suspended.

3 . The NVM device of claim 1 , wherein the read command comprises a plurality of dummy cycles added to allow time for the write operation to be suspended.

4 . The NVM device of claim 1 , wherein the read command comprises suspension of a clock signal to allow time for the write operation to be suspended.

5 . The NVM device of claim 1 , wherein the detection of the read command comprises detection of a transition of a chip select signal in the interface during the execution of the write operation.

6 . The NVM device of claim 1 , wherein the interface comprises an inter-integrated circuit (I2C) interface or a serial peripheral interface (SPI).

7 . The NVM device of claim 1 , wherein the suspension of the write operation comprises maintaining a plurality of biases associated with the write operation.

8 . The NVM device of claim 1 , further comprising a register that stores a configuration of the plurality of array planes.

9 . The NVM device of claim 1 , further comprising a progress counter configured to measure progress in completing the write operation.

10 . The NVM device of claim 1 , wherein each of the plurality of array planes contains an equal number of the plurality of NVM cells.

11 . The NVM device of claim 1 , wherein at least two of the plurality of array planes contain a different number of the plurality of NVM cells.

12 . The NVM device of claim 1 , wherein the memory array comprises a plurality of resistive memory cells, wherein each of the resistive memory cells is configured to be programmed to a low resistance state by application of a first voltage in a forward bias direction, and to be erased to a high resistance state by application of a second voltage in a reverse bias direction.

13 . The NVM device of claim 12 , wherein each of the resistive switching memory cells comprises a programmable impedance element, comprising:
a) an inert electrode coupled to a first side of a solid electrolyte; b) an active electrode coupled to a second side of the solid electrolyte, wherein the programmable impedance element is programmed by formation of a conductive path between the active and inert electrodes; and c) a plurality of mobile elements derived from the active electrode, wherein the plurality of mobile elements are reduced in the solid electrolyte to form the conductive path.

14 . A method of controlling a non-volatile memory (NVM) device, the method comprising:
a) receiving, by an interface, a write command from a host; b) beginning execution of a write operation on a first array plane of a memory array in response to the write command, wherein the memory array comprises a plurality of NVM cells arranged in a plurality of array planes; c) receiving, by the interface, a read command from the host; d) suspending the write operation in response to detection of the read command during execution of the write operation; e) beginning execution of a read operation on a second of the plurality of array planes in response to the read command; and f) resuming the write operation after the read operation has at least partially been executed.

15 . The method of claim 14 , wherein the receiving the read command comprises receiving a plurality of clock cycles added to allow time for the write operation to be suspended.

16 . The method of claim 14 , wherein the receiving the read command comprises receiving a plurality of dummy cycles added to allow time for the write operation to be suspended.

17 . The method of claim 14 , wherein the receiving the read command comprises suspending a clock signal to allow time for the write operation to be suspended.

18 . The method of claim 14 , wherein the detection of the read command comprises detection of a transition of a chip select signal in the interface during the execution of the write operation.

19 . The method of claim 14 , wherein the suspending the write operation comprises maintaining a plurality of biases associated with the write operation.

20 . The method of claim 14 , wherein the interface comprises a serial peripheral interface (SPI) or an inter-integrated circuit (I2C) interface.

Assignees

• Adesto Technologies Corp

Inventors

• Intrater Gideon
• Pedersen Bard
• Hollmer Shane
• Lewis Derric
• Trinh Stephen

Classifications

• G11C13/0011

  comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs] · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C2216/20

  Suspension of programming or erasing cells in an array in order to read other cells in it · CPC title