Suspending translation look-aside buffer purge execution in a multi-processor environment

Patent metadata

Field	Value
Publication number	US-10248575-B2
Application number	US-201815899963-A
Country	US
Kind code	B2
Filing date	Feb 20, 2018
Priority date	Jun 16, 2017
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

Disclosed herein is a method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.

First claim

What is claimed is:

1. A method for operating translation look-aside buffers, TLBs, in a multiprocessor system, the multiprocessor system comprising at least one core each supporting at least one thread, the method comprising:
receiving a purge request for purging one or more entries in the TLB;
determining if a thread requires access to an entry of the entries to be purged;
when the thread does not require access to the entries to be purged:
starting execution of the purge request in the TLB;
setting a suspension time window wherein the setting of the suspension time window is performed in response to an address translation request of the thread being rejected due to the TLB purge, wherein setting further comprises providing a level signal having a predefined activation time period during which the level signal is active, wherein the suspension time window is the predefined activation time period, and wherein a rejected address translation request is recycled during a recycling time window, wherein the recycling time window is smaller than the suspension time window;
suspending the execution of the purge during the suspension time window;
executing address translation requests of the thread during the suspension time window wherein the executing of the address translation requests of the thread comprises executing the recycled address translation request;
resuming the purge execution after the suspension window is ended;

when the thread requires access to the entries to be purged:
providing a branch point having two states;
providing a second branch point having two states;
blocking the thread for preventing the thread sending address translation requests to the TLB with firmware instructions, wherein blocking the thread comprises setting the branch point to a first state, setting the second branch point to a third state, and reading the first state of the branch point, and reading the third state of the second branch point, for performing the blocking with firmware instructions;
upon ending the purge request execution,
setting the first branch point to a second state
unblocking the thread and executing the address translation requests of the thread;
wherein the at least one core supporting a second thread, and when a first thread does not require access to the TLB entries to be purged and the second thread requires access to an entry to be purged, before starting the execution of the purge request at the TLB:
blocking both the first and second threads for preventing them sending requests to the TLB; and
when the purge request has started at both the first and second threads, unblocking the first thread.

Assignees

• IBM

Inventors

• Brandt Uwe
• Gaertner Ute
• Heller Lisa C
• Helms Markus
• Köhler Thomas
• Lehnert Frank
• Navarro Jennifer A
• Wisniewski Rebecca S

Classifications

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F2212/65

  Details of virtual memory and virtual address translation · CPC title

• G06F2212/50

  Control mechanisms for virtual memory, cache or TLB · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/30

  Providing cache or TLB in specific location of a processing system · CPC title