Planar photonic switch fabrics with reduced waveguide crossings

Patent metadata

Field	Value
Publication number	US-10244296-B1
Application number	US-201715839309-A
Country	US
Kind code	B1
Filing date	Dec 12, 2017
Priority date	Dec 12, 2017
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

Techniques for using planar photonic switch fabrics with reduced waveguide crossings are described. In one embodiment, a system is provided that comprises a memory that stores computer-executable components and a processor that executes computer-executable components stored in the memory. In one implementation, the computer-executable components comprise an arrangement component that arranges a first planar switch fabric topology. The computer-executable components further comprise a transformation component that interleaves a plurality of inputs of the first planar switch fabric topology and a plurality of outputs of the first planar switch fabric topology to form a second planar switch fabric topology, the second planar switch fabric topology having a lower number of waveguide crossings than the first planar switch fabric topology.

First claim

What is claimed is:

1. A system, comprising:
a memory that stores computer executable components; and
a processor that executes the computer executable components stored in the memory, wherein the computer executable components comprise:
an arrangement component that arranges a first planar switch fabric topology; and
a waveguide routing component that routes a first waveguide of the first planar switch fabric topology around a perimeter of a first input/output (I/O) stage of the first planar switch fabric topology to produce a second planar switch fabric topology, the first I/O stage being located on an interior of the second planar switch fabric topology, the second planar switch fabric topology having a lower number of waveguide crossings than the first planar switch fabric topology;
wherein a signal, an input or a light wave is injected into the first I/O stage of the second planar switch fabric topology using a second waveguide located on a separate planar layer as the first waveguide; and
wherein a first layer of the second planar switch fabric topology is fabricated in a silicon layer, and a second layer of the second planar switch fabric topology that comprises the second waveguide is fabricated in silicon nitride.

2. The system of claim 1 , wherein the first I/O stage comprises an input stage or an output stage.

3. The system of claim 1 , wherein the second planar switch fabric topology comprises a data receiving optical detector that is integrated within an interior of the second planar switch fabric topology.

4. A computer-implemented method, comprising:
arranging, by a system operatively coupled to a processor, a first planar switch fabric topology; and
routing, by the system, a first waveguide of the first planar switch fabric topology around a perimeter of a first input/output (I/O) stage of the first planar switch fabric topology to produce a second planar switch fabric topology, the first I/O stage being located on an interior of the second planar switch fabric topology, the second planar switch fabric topology having a lower number of waveguide crossings than the first planar switch fabric topology; and
injecting by the system, a signal, an input or a light wave into the first I/O stage of the second planar switch fabric topology using a second waveguide located on a separate planar layer as the first waveguide, wherein a first layer of the second planar switch fabric topology is fabricated in a silicon layer, and a second layer of the second planar switch fabric topology that comprises the second waveguide is fabricated in silicon nitride.

5. The computer-implemented method of claim 4 , wherein the first I/O stage comprises an input stage or an output stage.

6. The computer-implemented method of claim 4 , wherein the second planar switch fabric topology comprises a data transmitting optical emitter that is integrated within an interior of the second planar switch fabric topology.

7. A computer program product that facilitates implementation of planar photonic switch fabrics with reduced waveguide crossings, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions being executable by a processor to cause the processor to:
arrange a first planar switch fabric topology; and
route a first waveguide of the first planar switch fabric topology around a perimeter of a first input/output (I/O) stage of the first planar switch fabric topology to produce a second planar switch fabric topology, the first I/O stage being located on an interior of the second planar switch fabric topology, the second planar switch fabric topology having a lower number of waveguide crossings than the first planar switch fabric topology;
wherein a signal, an input or a light wave is injected into the first I/O stage of the second planar switch fabric topology using a second waveguide located on a separate planar layer as the first waveguide; and
wherein a first layer of the second planar switch fabric topology is fabricated in an indium phosphide layer, and a second layer of the second planar switch fabric topology that comprises the second waveguide is fabricated in silicon nitride.

8. The computer program product of claim 7 , wherein the first I/O stage comprises an input stage or an output stage.

9. The computer program product of claim 7 , wherein the second planar switch fabric topology comprises a data receiving optical detector that is integrated within an interior of the second planar switch fabric topology.

Assignees

• IBM

Inventors

• Dupuis Nicolas
• Lee Benjamin

Classifications

• H04Q2011/0058

  Crossbar; Matrix · CPC title

• H04L49/30

  Peripheral units, e.g. input or output ports · CPC title

• H04Q11/0005 Primary

  Switch and router aspects · CPC title

• H04Q2011/0049

  Crosstalk reduction; Noise; Power budget · CPC title

• H04Q11/0062

  Network aspects · CPC title