Switch and select topology for photonic switch fabrics and a method and system for forming same

Patent metadata

Field	Value
Publication number	US-9602432-B2
Application number	US-201514750356-A
Country	US
Kind code	B2
Filing date	Jun 25, 2015
Priority date	Mar 20, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A method for generating a switch fabric topology, comprising constructing a first switch fabric topology, modifying the first switch fabric topology to generate a second switch fabric topology, wherein modifying the first switch fabric topology comprises isolating center stage sets of the first switch fabric topology, and replacing each of the isolated center stage sets with a single × switching element to generate the second switch fabric topology, wherein is an integer representing a radix of the switching element determined in connection with the constructing of the first switch fabric topology.

First claim

What is claimed is:

1. A computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:
constructing a first switch fabric topology; and
modifying the first switch fabric topology to generate a second switch fabric topology, wherein modifying the first switch fabric topology comprises:
isolating center stage sets of the first switch fabric topology; and
replacing each of the isolated center stage sets with a single × switching element to generate the second switch fabric topology;

wherein is an integer representing a radix of the switching element determined in connection with the constructing of the first switch fabric topology;
wherein each isolated center-stage set comprises 1× switching elements in a final stage of a plurality of input-port trees and ×1 switching elements in a first stage of a plurality of output-port trees; and
wherein the 1× switching elements are connected with the ×1 switching elements by 2 waveguides.

2. The computer program product according to claim 1 , wherein:
the first and second switch fabric topologies each comprise N input ports and M output ports, where N and M are integers; and
a number of the center stage sets replaced is given by N×M/( 2 ).

3. The computer program product according to claim 1 , wherein the first switch fabric topology comprises a switch-and-select topology.

4. The computer program product according to claim 1 , wherein the second switch fabric topology comprises less switches, less switch hops and less waveguide crossings than the first switch fabric topology.

5. A computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:
constructing a first switch fabric topology; and
modifying the first switch fabric topology to generate a second switch fabric topology, wherein modifying the first switch fabric topology comprises:
isolating center stage sets of the first switch fabric topology; and
replacing each of the isolated center stage sets with a single × switching element to generate the second switch fabric topology;

wherein is an integer representing a radix of the switching element determined in connection with the constructing of the first switch fabric topology; and
wherein constructing the first switch fabric topology comprises:
determining a number of input ports N and a number of output ports M for the first switch fabric topology, wherein N= and M= l , and N, M, and l are integers;
for each of the N input ports, generating an C-stage branching-out tree constructed from 1× switching elements;
for each of the M output ports, generating a -stage branching-in tree constructed from ×1 switching elements; and
connecting an m th output of an n th branching-out tree to an n th input of an m th branching-in tree, wherein m=integers from 1 to M, and n=integers from 1 to N.

6. An apparatus, comprising:
a memory; and
a processing device operatively coupled to the memory and configured to:
construct a first switch fabric topology; and
modify the first switch fabric topology to generate a second switch fabric topology, wherein modifying the first switch fabric topology comprises:
isolating center stage sets of the first switch fabric topology; and
replacing each of the isolated center stage sets with a single × switching element to generate the second switch fabric topology;

wherein is an integer representing a radix of the switching element determined in connection with constructing the first switch fabric topology;
wherein each isolated center-stage set comprises 1× switching elements in a final stage of a plurality of input-port trees and ×1 switching elements in a first stage of a plurality of output-port trees; and
wherein the 1× switching elements are connected with the ×1 switching elements by 2 waveguides.

7. The apparatus according to claim 6 , wherein:
the first and second switch fabric topologies each comprise N input ports and M output ports, where N and M are integers; and
a number of the center stage sets replaced is given by N×M/( 2 ).

8. An apparatus comprising:
a memory; and
a processing device operatively coupled to the memory and configured to:
construct a first switch fabric topology; and
modify the first switch fabric topology to generate a second switch fabric topology, wherein modifying the first switch fabric topology comprises:
isolating center stage sets of the first switch fabric topology; and
replacing each of the isolated center stage sets with a single × switching element to generate the second switch fabric topology;

wherein is an integer representing a radix of the switching element determined in connection with constructing the first switch fabric topology; and
wherein constructing the first switch fabric topology comprises:
determining a number of input ports N and a number of output ports M for the first switch fabric topology, wherein N= and M= l , and N, M, and l are integers;
for each of the N input ports, generating an l-stage branching-out tree constructed from 1× switching elements;
for each of the M output ports, generating a -stage branching-in tree constructed from ×1 switching elements; and
connecting an m th output of an n th branching-out tree to an n th input of an m th branching-in tree, wherein m=integers from 1 to M, and n=integers from 1 to N.

Assignees

• IBM

Inventors

• Lee Benjamin G
• Minkenberg Cyriel J

Classifications

• H04L45/02

  Topology update or discovery · CPC title

• H04L49/10 Primary

  characterised by the switching fabric construction · CPC title

• H04L49/30

  Peripheral units, e.g. input or output ports · CPC title

• H04Q11/0062

  Network aspects · CPC title

• H04Q2011/009

  Topology aspects · CPC title