Method for producing optoelectronic devices and surface-mountable optoelectronic device

US10243117B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10243117-B2
Application numberUS-201615573820-A
CountryUS
Kind codeB2
Filing dateMay 11, 2016
Priority dateMay 13, 2015
Publication dateMar 26, 2019
Grant dateMar 26, 2019

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method for producing optoelectronic devices and a surface-mountable optoelectronic device are disclosed. In an embodiment the method includes applying semiconductor chips laterally adjacent one another on a carrier, wherein contact sides of the chips face the carrier, and wherein each semiconductor chip comprises contact elements for external electrical contacting which are arranged on the contact side of the semiconductor chip and applying an electrically conductive layer on at least sub-regions of the sides of the semiconductor chips not covered by the carrier, wherein the electrically conductive layer is formed contiguously, and wherein protective elements prevent direct contact of the contact elements with the electrically conductive layer. The method further includes electrophoretically depositing a converter layer on the electrically conductive layer and removing the electrically conductive layer from regions between the converter layer and the semiconductor chips.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for producing optoelectronic devices, the method comprising: A) providing a carrier and a plurality of optoelectronic semiconductor chips, wherein each semiconductor chip comprises contact elements for external electrical contacting which are arranged on a contact side of the semiconductor chip; B) applying the semiconductor chips laterally adjacent one another on the carrier, wherein the contact sides face the carrier and the contact elements are laterally surrounded by protective elements; C) applying an electrically conductive layer on at least sub-regions of the sides of the semiconductor chips not covered by the carrier, wherein the electrically conductive layer is formed contiguously, and wherein the protective elements prevent direct contact of the contact elements with the electrically conductive layer; D) electrophoretically depositing a converter layer on the electrically conductive layer, wherein the converter layer is configured to convert at least a proportion of radiation emitted by the semiconductor chips into radiation of another wavelength range; and E) removing the electrically conductive layer from regions between the converter layer and the semiconductor chips, wherein, before step C), a potting compound is introduced between the semiconductor chips, wherein the potting compound partially or completely covers side faces of the semiconductor chips which extend transversely on the contact side, wherein radiation sides opposite the contact sides remain partially or completely free of the potting compound, wherein, in step C), the electrically conductive layer is applied to the potting compound located between the semiconductor chips, and wherein, in step E), the electrically conductive layer is removed from regions between the converter layer and the potting compound. 2. The method according to claim 1 , wherein steps A) to E) are preformed in the stated sequence in succession and mutually independently, wherein a bonding layer is applied to the carrier, wherein during step B) the contact elements are pressed deeply enough into the bonding layer so that, in step C), the contact elements are protected from being covered with the electrically conductive layer, wherein the bonding layer comprises a thermoplastic material, and wherein, after step E), the semiconductor chips are detached from the carrier and singulated. 3. The method according to claim 1 , wherein the electrically conductive layer and/or the converter layer continuously, contiguously and uninterruptedly extend over all the sides of the semiconductor chips not concealed by the carrier and at least 90% conceal these sides. 4. The method according to claim 1 , wherein the carrier is a potting material in which the semiconductor chips are embedded so that steps A) and B) constitute a single, common step, wherein, after steps A) and B), the semiconductor chips are embedded in the potting material in such a manner that the contact sides are completely covered by the potting material, side faces of the semiconductor chips extending transversely of the contact side are partially or completely covered by the potting material, and radiation sides opposite the contact sides are partially or completely free of the potting material, wherein, after step E), holes, through which the contact elements are electrically connected, are introduced into the potting material. 5. The method according to claim 1 , wherein, in step E), the electrically conductive layer is removed by a wet chemical process, wherein the electrically conductive layer comprises at least one metal or is formed from at least one metal, wherein, in step E), the metal is partially or completely converted by chemical reaction into a salt of the metal, and wherein, after step E), a mole fraction of the salt in the converter layer amounts to between 0.001% and 2% inclusive. 6. The method according to claim 1 , wherein the converter layer has a uniform layer thickness with maximum thickness fluctuations of 5% about a mean layer thickness along the entire extent on the semiconductor chips, wherein, after step E), the layer thickness of the converter layer amounts to at most 70 μm, and wherein, after step E), the converter layer extends continuously, contiguously and uninterruptedly on the semiconductor chips. 7. The method according to claim 1 , wherein, the converter layer comprises a powder of converter particles, and wherein, after step E), the converter layer is surrounded with an encapsulation layer which prevents detachment, crumbling or flaking of the converter layer from the semiconductor chips. 8. The method according to claim 7 , wherein the encapsulation layer comprises a transparent material which is at least 90% transmissive to the radiation emitted by the semiconductor chips and/or by the converter layer, and wherein, after step E), the encapsulation layer is patterned comprising a plurality of lenses, wherein a portion of the patterned encapsulation layer acts as a lens for radiation emitted by the respective semiconductor chip. 9. The method according to claim 1 , wherein the carrier is a printed circuit board to which the semiconductor chips are electrically connected and mechanically fastened. 10. The method according to claim 1 , wherein a protective frame for each semiconductor chip is applied to the carrier, wherein, during step B), the semiconductor chips are placed on the carrier in such a manner that the contact elements are at least partially surrounded by the corresponding protective frame, and wherein the protective frames prevent the contact elements from being covered with the electrically conductive layer in step C). 11. The method according to claim 1 , wherein the semiconductor chips are sapphire flip chips in each case comprising a sapphire growth substrate which stabilizes the semiconductor chip and a semiconductor layer sequence grown on the sapphire growth substrate, and wherein the contact elements are arranged on a side of the semiconductor layer sequence remote from the sapphire growth substrate. 12. The method according to claim 1 , wherein the semiconductor chips are thin-film semiconductor chips in each case comprising a substrate which stabilizes the semiconductor chip and a semiconductor layer sequence applied to the substrate, wherein the substrate differs from a growth substrate of the semiconductor layer sequence and the growth substrate is removed from the semiconductor chip, and wherein the contact elements are applied to a side of the substrate remote from the semiconductor layer sequence. 13. A surface-mountable optoelectronic device comprising: an optoelectronic semiconductor chip with uncovered contact elements for external electrical contacting of the device, wherein the contact elements are arranged on a common contact side of the semiconductor chip; a continuous, contiguous and uninterrupted converter layer which at least 90% conceals a radiation side of the semiconductor chip which is opposite the contact side; and an encapsulation layer which is applied to the converter layer and completely conceals and encloses the converter layer, wherein the converter layer is configured to convert at least a proportion of radiation emitted by the semiconductor chip into radiation of another wavelength range, wherein the converter layer has a uniform layer thickness with maximum thickness fluctuations of 5% about a mean layer thickness along an entire extent on the semiconductor chip, wherein the layer thickness of the converter layer amounts to at most 70 μm, wherein the converter laye

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10243117B2 cover?
A method for producing optoelectronic devices and a surface-mountable optoelectronic device are disclosed. In an embodiment the method includes applying semiconductor chips laterally adjacent one another on a carrier, wherein contact sides of the chips face the carrier, and wherein each semiconductor chip comprises contact elements for external electrical contacting which are arranged on the co…
Who is the assignee on this patent?
Osram Opto Semiconductors Gmbh
What technology area does this patent fall under?
Primary CPC classification C25D13/02. Mapped technology areas include Chemistry & Metallurgy.
When was this patent published?
Publication date Tue Mar 26 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).