Rework of patterned dielectric and metal hardmask films

Patent metadata

Field	Value
Publication number	US-10242872-B2
Application number	US-201715464758-A
Country	US
Kind code	B2
Filing date	Mar 21, 2017
Priority date	Mar 21, 2017
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A method for reworking a semiconductor device includes, in a pattern stack formed on an interlevel dielectric (ILD) layer, polishing the pattern stack to remove a top hardmask layer of the pattern stack. Each hardmask layer of the pattern stack is selectively wet etched to remaining layers of the pattern stack and the ILD layer. A reworked pattern stack is reformed on the ILD layer.

First claim

What is claimed is:

1. A method for reworking a semiconductor device, comprising:
in response to evaluating a pattern failure in a pattern stack formed on an interlevel dielectric (ILD) layer, polishing the pattern stack disposed on an interlevel dielectric (ILD) layer to remove a top hardmask layer of the pattern stack;
wet etching a next hardmask layer of the pattern stack selectively to one or more remaining layers of the pattern stack and the ILD layer;
wet etching the one or more remaining layers of the pattern stack selectively to the ILD layer to expose the ILD layer; and
forming a reworked pattern stack on the ILD layer.

2. The method as recited in claim 1 , further comprising evaluating a pattern failure of the pattern stack including at least one of increased defectivity, an out of specification critical dimension or layer misalignment.

3. The method as recited in claim 1 , wherein polishing the pattern stack includes chemical mechanical polishing the top hardmask layer selectively to an underlying layer in the pattern stack.

4. The method as recited in claim 1 , wherein the wet etching steps include a different wet etch chemistry for each step.

5. The method as recited in claim 1 , wherein the wet etching steps include a same wet etch chemistry.

6. The method as recited in claim 1 , further comprising checking a thickness of the ILD layer to determine suitability for rework processing.

7. The method as recited in claim 1 , wherein forming the reworked pattern stack on the ILD layer includes depositing a bottom hardmask layer and at least one other hardmask layer over the ILD layer.

8. The method as recited in claim 1 , wherein the pattern stack includes a dielectric bottom dielectric hardmask layer, a metal hardmask layer formed on the bottom dielectric hardmask layer and the top hardmask layer formed on the metal hardmask layer.

9. The method as recited in claim 1 , wherein forming the reworked pattern stack includes reworking the pattern stack two or more times.

10. A method for reworking a semiconductor device, comprising:
evaluating a pattern failure in a pattern stack formed on an interlevel dielectric (ILD) layer;
polishing the pattern stack to remove a top hardmask layer of the pattern stack;
wet etching a next hardmask layer of the pattern stack selectively to remaining layers of the pattern stack and the ILD layer;
wet etching the pattern stack selectively to the ILD layer to expose the ILD layer; and
forming a reworked pattern stack on the ILD layer.

11. The method as recited in claim 10 , wherein evaluating the pattern failure includes at least one of increased defectivity, an out of specification critical dimension, and layer misalignment.

12. The method as recited in claim 10 , wherein polishing the pattern stack includes chemical mechanical polishing the top hardmask layer selectively to an underlying layer in the pattern stack.

13. The method as recited in claim 10 , wherein the wet etching steps include a different wet etch chemistry for each step.

14. The method as recited in claim 10 , wherein the wet etching steps include a same wet etch chemistry.

15. The method as recited in claim 10 , further comprising checking a thickness of the ILD layer to determine suitability for rework processing.

16. The method as recited in claim 10 , wherein forming the reworked pattern stack on the ILD layer includes depositing a bottom hardmask layer and at least one other hardmask layer over the ILD layer.

17. The method as recited in claim 10 , wherein the pattern stack includes a dielectric bottom dielectric hardmask layer, a metal hardmask layer formed on the bottom dielectric hardmask layer and the top hardmask layer formed on the metal hardmask layer.

18. The method as recited in claim 10 , wherein forming the reworked pattern stack includes reworking the pattern stack two or more times.

19. A method for reworking a semiconductor device, comprising:
chemical mechanical polishing the top hardmask layer selectively to an underlying layer in a misprocessed pattern stack having three or more layers formed on an interlevel dielectric (ILD) layer to remove a top hardmask layer of the pattern stack;
wet etching a metal hardmask layer of the pattern stack selectively to a bottom hardmask layer of the pattern stack and the ILD layer;
wet etching the pattern stack selectively to the ILD layer to expose the ILD layer by removing the bottom hardmask layer, wherein at least two of the three or more layers and the ILD layer include a similar etch behavior; and
forming a reworked pattern stack on the ILD layer.

20. The method as recited in claim 19 , wherein the pattern failure includes at least one of increased defectivity, an out of specification critical dimension, and layer misalignment.

21. The method as recited in claim 19 , wherein the wet etching steps include a different wet etch chemistry for each step.

22. The method as recited in claim 19 , wherein the wet etching steps include a same wet etch chemistry.

23. The method as recited in claim 19 , further comprising checking a thickness of the ILD layer to determine suitability for rework processing.

24. The method as recited in claim 19 , wherein forming the reworked pattern stack on the ILD layer includes depositing a bottom hardmask layer and at least one other hardmask layer over the ILD layer.

25. The method as recited in claim 19 , wherein forming the reworked pattern stack includes reworking the pattern stack two or more times.

Assignees

• IBM

Inventors

• Arnold John C
• Bhosale Prasad
• Canaperi Donald F
• Patlolla Raghuveer R
• Peethala Cornelius B
• Shobha Hosadurga
• Standaert Theodorus E

Classifications

• H10P95/062 Primary

  involving a dielectric removal step · CPC title

• H10P76/4083

  characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P50/667

  by liquid etching only · CPC title