Digital on-chip duty cycle monitoring device

Patent metadata

Field	Value
Publication number	US-10241537-B2
Application number	US-201715622350-A
Country	US
Kind code	B2
Filing date	Jun 14, 2017
Priority date	Jun 14, 2017
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

An apparatus includes an oscillator circuit, a counter circuit, and a control circuit. The oscillator circuit may receive an input clock signal and an inverse input clock signal, and, for a first time period, may generate an oscillator output signal with a frequency based on a duty cycle of the input clock signal. For a second time period, the oscillator circuit may generate the oscillator output signal with a frequency based on a duty cycle of the inverse input clock signal. The counter circuit may count oscillations of the oscillator output signal over the first time period and over the second time period. The control circuit may determine, based on the oscillations counted by the counter circuit during the first time period and the second time period, a duty cycle value indicative of the duty cycle of the input clock signal.

First claim

What is claimed is:

1. An apparatus, comprising:
an oscillator circuit configured to:
receive an input clock signal and an inverse input clock signal; and
for a first time period, generate an oscillator output signal with a frequency based on a duty cycle of the input clock signal; and
for a second time period, generate the oscillator output signal with a frequency based on a duty cycle of the inverse input clock signal;

a counter circuit configured to count oscillations of the oscillator output signal over the first time period and over the second time period; and
a control circuit configured to determine, based on the oscillations counted by the counter circuit during the first time period and the second time period, a duty cycle value indicative of the duty cycle of the input clock signal.

2. The apparatus of claim 1 , further comprising a duty cycle adjustment circuit configured to compare the duty cycle value to an expected value.

3. The apparatus of claim 2 , wherein the duty cycle adjustment circuit is further configured to modify a duty cycle of the input clock signal based on the comparison.

4. The apparatus of claim 2 , further comprising a processor configured to determine and set the expected value based on a desired duty cycle for the input clock signal.

5. The apparatus of claim 1 , wherein the counter circuit is further configured to:
increment a count value during the first time period; and
decrement the count value during the second time period, wherein the second time period is subsequent to the first time period.

6. The apparatus of claim 1 , wherein a length of the first time period and a length of the second time period are programmable.

7. The apparatus of claim 1 , wherein the control circuit is further configured to receive a first value corresponding to a length of the first time period and a second value corresponding to a length of the second time period, and wherein the first and second values are selected based on a desired duty cycle for the input clock signal.

8. An apparatus, comprising:
an oscillator circuit configured to:
receive an input clock signal and an inverse input clock signal;
generate a first oscillator output signal with a frequency based on a duty cycle of the input clock signal; and
generate a second oscillator output signal with a frequency based on a duty cycle of the inverse input clock signal;

a counter circuit configured to:
count oscillations of the first oscillator output signal for a specified time period; and
count oscillations of the second oscillator output signal for the specified time period; and

a control circuit configured to determine, based on the oscillations counted by the counter circuit for the specified time period, a duty cycle value indicative of the duty cycle of the input clock signal.

9. The apparatus of claim 8 , further comprising a duty cycle adjustment circuit configured to compare the duty cycle value to an expected value.

10. The apparatus of claim 9 , wherein the duty cycle adjustment circuit is further configured to modify a duty cycle of the input clock signal based on the comparison.

11. The apparatus of claim 9 , further comprising a processor configured to determine and set the expected value based on a desired duty cycle for the input clock signal.

12. The apparatus of claim 8 , wherein to count oscillations of the first oscillator output signal and the second oscillator output signal, the counter circuit is further configured to increment a first count value and a second count value during the specified time period.

13. The apparatus of claim 12 , wherein to determine, based on the oscillations counted by the counter circuit during the specified time period, the duty cycle value, the control circuit is further configured to subtract the second count value from the first count value.

14. The apparatus of claim 12 , wherein initial count values for the first count value and the second count value are programmable.

15. A system, comprising:
a reference clock generator configured to generate a reference clock signal;
a clock generation circuit, including a delay circuit, configured to generate a delayed clock signal based on the reference clock signal, wherein an amount of delay from the reference clock signal to the delayed clock signal is based on the delay circuit;
a logic circuit configured to generate a composite signal based on the reference clock signal and the delayed clock signal; and
a duty cycle monitor circuit configured to:
receive the composite signal;
generate an inverse composite signal;
generate an oscillator output signal, wherein a frequency of the oscillator output signal is based on a duty cycle of a selected one of the composite signal or the inverse composite signal;
count oscillations of the oscillator output signal for a first specified time period with the composite signal selected;
count oscillations of the oscillator output signal for a second specified time period with the inverse composite signal selected; and
determine, based on the oscillations counted during the first specified time period and the second specified time period, a duty cycle value indicative of the duty cycle of the composite signal.

16. The system of claim 15 , further including a control circuit configured to calibrate the delay circuit based on the duty cycle value.

17. The system of claim 15 , wherein to count oscillations of the oscillator output signal for the first specified time period, the duty cycle monitor circuit is further configured to increment a count value during the first specified time period.

18. The system of claim 17 , wherein to count oscillations of the oscillator output signal for the second specified time period, the duty cycle monitor circuit is further configured to decrement the count value during the second specified time period, wherein the second specified time period is subsequent to the first specified time period.

19. The system of claim 18 , wherein a length of the first specified time period and a length of the second specified time period are programmable and are determined based on a desired duty cycle for the composite signal.

20. The system of claim 15 , wherein the duty cycle of the composite signal is indicative of the amount of delay of the delay circuit.

Assignees

• Apple Inc

Inventors

• Li Huaimin
• Faure Fabien S
• Hamami Shy
• Trivedi Pradeep
• Cohen Yaron

Classifications

• H03K21/08

  Output circuits · CPC title

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• H03K2005/00019

  Variable delay · CPC title

• H03K5/04

  by increasing duration; by decreasing duration · CPC title