Digital duty cycle correction

Patent metadata

Field	Value
Publication number	US-9236853-B2
Application number	US-201414172758-A
Country	US
Kind code	B2
Filing date	Feb 4, 2014
Priority date	Feb 4, 2014
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A digital duty-cycle correction circuit may include an adjustment unit that may be configured to adjust a duty cycle of an oscillating signal based on an adjust signal to generate an adjusted oscillating signal and a sampling unit that may be configured to sample the adjusted oscillating signal. The circuit may also include a counting unit that may be configured to generate an indication of a number of samples of the adjusted oscillating signal that are at the low and high level and to adjust the indication using a selectable duty cycle modify signal based on a desired duty cycle of the adjusting oscillating signal. The circuit may also include a comparing and filtering unit that may be configured to generate the adjust signal based on a comparison of the indication with a comparison count. The indication may be adjustable such that the oscillating signal's duty cycle is adjustable.

First claim

What is claimed is:

1. A digital duty-cycle correction circuit comprising:
an adjustment unit configured to adjust a duty cycle of an oscillating signal based on an adjust signal to generate an adjusted oscillating signal, the oscillating signal configured to oscillate between a low level and a high level;
a sampling unit configured to sample the adjusted oscillating signal;
a counting unit configured to generate an indication of a number of samples of the adjusted oscillating signal that are at the low level and a number of samples of the adjusted oscillating signal that are at the high level and to adjust the indication using a selectable duty cycle modify signal based on a desired duty cycle of the adjusted oscillating signal such that the duty cycle of the oscillating signal is adjustable to more than one value; and
a comparing and filtering unit configured to generate the adjust signal based on a comparison of the indication with a comparison count.

2. The circuit of claim 1 , wherein the oscillating signal is a differential signal that includes first and second complementary signals.

3. The circuit of claim 2 , wherein the sampling unit is configured to sample the adjusted first and second complementary signals using a single register.

4. The circuit of claim 3 , wherein the indication generated by the counting unit is a count output by the counting unit, the count being increased when the first complementary signal is sampled at the high level and the count being decreased when the second complementary signal is sampled at the high level.

5. The circuit of claim 1 , wherein the count stabilizes or dithers around a middle value of the counting unit when the duty cycle of the adjusted oscillating signal is the desired duty cycle.

6. The circuit of claim 1 , wherein the sampling unit is configured to sample the adjusted oscillating signal at a sampling rate that is lower than an oscillating rate of the adjusted oscillating signal.

7. The circuit of claim 1 , wherein the comparing and filtering unit includes a comparing circuit configured to assert a first signal when the indication is more than the comparison count and to assert a second signal when the indication is less than the comparison count.

8. The circuit of claim 7 , wherein the comparing and filtering unit further includes a digital filter coupled to the comparing circuit and configured to generate the adjust signal based on the first and second signals.

9. The circuit of claim 8 , wherein the digital filter is clocked slower than a sampling rate of the sampling unit.

10. The circuit of claim 8 , further comprising a lock detector circuit configured to generate a locking signal based on the first and second signals when the duty cycle of the adjusted oscillating signal approximates the desired duty cycle and to send the locking signal to the digital filter, the digital filter configured to ignore the first and second signals and to maintain the adjust signal after receiving the locking signal.

11. A digital duty-cycle correction circuit comprising:
an adjustment unit configured to adjust a duty cycle of an oscillating signal based on an adjust signal to generate an adjusted oscillating signal, the oscillating signal configured to oscillate between a low level and a high level;
a sampling unit configured to sample the adjusted oscillating signal;
a counting unit configured to generate an indication of a number of samples of the adjusted oscillating signal that are at the low level and a number of samples of the adjusted oscillating signal that are at the high level and to adjust the indication using a selectable duty cycle modify signal based on a desired duty cycle of the adjusted oscillating signal;
a comparing circuit configured to generate a comparison signal based on a comparison of the indication with a comparison count;
a lock detector configured to determine when the duty cycle of the adjusted oscillating signal approximates the desired duty cycle of the adjusted oscillating signal and to generate a locking signal based on the determination; and
a digital filter configured to generate the adjust signal based on the comparison signal when the locking signal is a first value and to maintain a previously generated adjust signal when the locking signal is a second value.

12. The circuit of claim 11 , wherein the digital filter is clocked slower than a sampling rate used by the counting unit to sample the adjusted oscillating signal.

13. The circuit of claim 12 , wherein the sampling rate is lower than an oscillating rate of the adjusted oscillating signal.

14. The circuit of claim 12 , wherein the adjusted oscillating signal is a differential clock signal that includes adjusted first and second complementary signals and the indication generated by the counting unit is a count output by the counting unit, the count being increased when the adjusted first complementary signal is sampled at the high level, the count being decreased when the adjusted second complementary signal is sampled at the high level, and the count being biased by the duty cycle modify signal.

15. A method of correcting a duty cycle of an oscillating signal, the method comprising:
adjusting a duty cycle of an oscillating signal based on an adjust signal to generate an adjusted oscillating signal, the oscillating signal configured to oscillate between a low level and a high level;
sampling the adjusted oscillating signal;
generating an indication of a number of samples of the adjusted oscillating signal that are at the low level and a number of samples of the adjusted oscillating signal that are at the high level;
adjusting the indication using a selectable duty cycle modify signal based on a desired duty cycle of the adjusted oscillating signal such that the duty cycle of the oscillating signal is adjustable to more than one value;
comparing the indication with a comparison count; and
generating the adjust signal based on the comparison of the indication with the comparison count.

16. The method of claim 15 , wherein the adjusted oscillating signal is sampled at a sampling rate that is lower than an oscillating rate of the adjusted oscillating signal.

17. The method of claim 15 , wherein the adjusted oscillating signal is a differential clock signal that includes adjusted first and second complementary signals, wherein sampling the level of the adjusted oscillating signal includes sampling the level of the adjusted first and second complementary signals.

18. The method of claim 17 , wherein the indication is a count, the count being increased when the adjusted first complementary signal is sampled at the high level and the count being decreased when the adjusted second complementary signal is sampled at the high level.

19. The method of claim 17 , wherein the indication is generated by a counter, the method further comprising determining the comparison count based on a counting range of the counter.

20. The method of claim 15 , further comprising locking the adjust signal when the duty cycle of the adjusted oscillating signal approximates the desired duty cycle of the adjusted oscillating signal.

Assignees

• Fujitsu Ltd

Inventors

• Walker William W

Classifications

• H03K19/0016

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• G01R27/02

  Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant (by measuring phase angle only G01R25/00) · CPC title

• G01R27/2605

  Measuring capacitance (capacitive sensors G01D5/24) · CPC title

• H03K21/00

  Details of pulse counters or frequency dividers · CPC title

• H03K5/05 Primary

  by the use of clock signals or other time reference signals · CPC title