Event-driven clock duty cycle control

Patent metadata

Field	Value
Publication number	US-9564885-B2
Application number	US-201214361575-A
Country	US
Kind code	B2
Filing date	Nov 16, 2012
Priority date	Dec 5, 2011
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

Duty cycle error vectors that indicate both the magnitude and direction of the duty cycle error relative to a desired duty cycle are generated within a duty cycle measurement circuit, enabling threshold-based determination of whether duty cycle adjustment is necessary, refraining from power-consuming adjustment and follow-up measurement in those cases where the duty cycle is within a target range. When duty cycle adjustment is deemed necessary, the magnitude of the duty cycle error indicated by the duty cycle error vector may be applied to effect proportional rather than incremental duty cycle adjustment, quickly returning the clock duty cycle to a target range.

First claim

What is claimed is:

1. A method of controlling duty cycle of a clock signal, the method comprising:
measuring a difference between durations of high and low phases of the clock signal;
generating a time-varying reference value representative of a period of the clock signal;
generating, as an error value, a ratio of the difference and the time-varying reference value such that the error value indicates a magnitude of the difference in relation to the period of the clock signal; and
adjusting the duty cycle of the clock signal if the magnitude exceeds an error threshold.

2. The method of claim 1 wherein generating the time-varying reference value representative of the period of the clock signal comprises measuring a difference between high and low phases of a reference signal over a measurement interval defined by a pair of rising edges of the clock signal or a pair of falling edges of the clock signal.

3. The method of claim 2 wherein the reference signal is a steady-state signal in which only one of the high and low phases of the reference signal has a nonzero duration such that the difference between the high and low phases of the reference signal corresponds to a maximum measurable difference over the measurement interval.

4. The method of claim 1 wherein generating the time-varying reference value representative of the period of the clock signal comprises looking up the reference value in a look-up table, including indexing the lookup table based, at least in part, on at least one of a temperature indication or a voltage indication.

5. The method of claim 1 further comprising storing a first threshold value within a programmable storage register to establish the error threshold.

6. The method of claim 1 wherein adjusting the duty cycle of the clock signal if the magnitude exceeds an error threshold comprises adjusting the duty cycle of the clock signal in proportion to the magnitude in response to determining that the magnitude exceeds the error threshold.

7. The method of claim 1 wherein measuring the difference between durations of high and low phases of the clock signal comprises:
generating a first pulse stream that pulses at a first rate when the clock signal is in a first logic state and at a second rate when the clock signal is in a second logic state;
counting the pulses in the first pulse stream over a first measurement interval to produce a first count value.

8. The method of claim 7 wherein measuring the difference between durations of high and low phases of the clock signal further comprises:
generating a second pulse stream that pulses at the second rate when the clock signal is in the first logic state and at the first rate when the clock signal is in the second logic state;
counting the pulses in the second pulse stream over a first time interval equal in duration to the first measurement interval to produce a second count value; and
subtracting the second count value from the first count value to produce a value corresponding to the difference between the durations of the high and low phases of the clock signal.

9. The method of claim 8 wherein generating the time-varying reference value representative of the period of the clock signal comprises:
generating a third pulse stream that pulses at the first rate;
counting pulses in the third pulse stream over a second time interval equal in duration to the first measurement interval to produce a third count value;
generating a fourth pulse stream that pulses at the second rate; and
counting pulses in the fourth pulse stream over a third time interval equal in duration to the first measurement interval to produce a fourth count value, subtracting the fourth count value from the third count value to produce the reference value.

10. The method of claim 1 wherein measuring the difference between durations of high and low phases of the clock signal comprises:
generating a first pulse stream;
during a first measurement interval, counting pulses in the first pulse stream when the clock signal is in a first logic state to produce a first count value;
generating a second pulse stream;
over a time interval equal in duration to the first measurement interval, counting pulses in the second pulse stream when the clock signal is in a second logic state to produce a second count; and
subtracting the second count value from the first count value to produce a value corresponding to the difference between the durations of the high and low phases of the clock signal.

11. An integrated circuit device comprising:
duty cycle measurement logic to measure a difference between durations of high and low phases of the clock signal;
reference value logic to generate a time-varying reference value representative of a period of the clock signal;
ratio logic to generate, as an error value, a ratio of the difference and the time-varying reference value such that the error value indicates a magnitude of the difference in relation to the period of the clock signal; and
duty cycle adjustment circuitry to adjust the duty cycle of the clock signal if the magnitude exceeds an error threshold.

12. The integrated circuit device of claim 11 wherein the reference value logic comprises circuitry to measure a difference between high and low phases of a reference signal over a measurement interval defined by a pair of rising edges of the clock signal or a pair of falling edges of the clock signal.

13. The integrated circuit device of claim 11 reference value logic comprises a lookup table and logic to retrieve the reference value from the lookup table based, at least in part, on at least one of a temperature indication or a voltage indication.

14. The integrated circuit device of claim 11 further comprising a programmable storage register to store a control value that establishes the error threshold.

15. The integrated circuit device of claim 11 wherein the duty cycle adjustment circuitry to adjust the duty cycle of the clock signal comprises circuitry to adjust the duty cycle of the clock signal in proportion to the magnitude in response to determining that the magnitude exceeds the error threshold.

16. The integrated circuit device of claim 11 wherein the duty cycle measurement logic to measure a difference between durations of high and low phases of the clock signal comprises circuitry to generate a first pulse stream that pulses at a first rate when the clock signal is in a first logic state and at a second rate when the clock signal is in a second logic state, and to count the pulses in the first pulse stream over a first measurement interval to produce a first count value.

17. The integrated circuit device of claim 16 wherein the duty cycle measurement logic further comprises circuitry to (i) generate a second pulse stream that pulses at the second rate when the clock signal is in the first logic state and at the first rate when the clock signal is in the second logic state, (ii) count the pulses in the second pulse stream over a first time interval equal in duration to the first measurement interval to produce a second count value, and (iii) subtract the second count value from the first count value to produce a value corresponding to the difference between the durations of the high and low phases of the clock signal.

18. The integrated circuit device of claim 17 wherein the reference value logic comprises circuitry to (i) generate a third pulse stream that pulses at the first rate, and count the pulses in the third pulse stream over a second time interval equal in duration to the first measure

Assignees

• Rambus Inc

Inventors

• Chau Pak Shing
• Richardson Wayne S
• Kim Jun

Classifications

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title