Electro-optic modulator with a periodic junction arrangement

US10241354B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-10241354-B1
Application numberUS-201815920785-A
CountryUS
Kind codeB1
Filing dateMar 14, 2018
Priority dateMar 14, 2018
Publication dateMar 26, 2019
Grant dateMar 26, 2019

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Techniques regard electro-optic modulators are provided. For example, one or embodiments described herein can regard an apparatus that can comprise a first lateral region, a second lateral region, and a central region located on a semiconductor substrate. The first lateral region can be adjacent to a first side of the central region and can have a first conductivity type. The second lateral region can be adjacent to a second side of the central region and can have a second conductivity type. Also, the first side can be opposite to the second side. Further, the central region can comprise a diode junction adjacent to an intrinsic region. The intrinsic region can separate the first lateral region and the second lateral region.

First claim

Opening claim text (preview).

What is claimed is: 1. An electro-optic modulator apparatus comprising: an optical waveguide extending along a longitudinal direction; and a first lateral region, a second lateral region, and a central region located on a semiconductor substrate and extending along a first direction transverse to the longitudinal direction, the first lateral region being adjacent to a first side of the central region and having a first conductivity type, the second lateral region being adjacent to a second side of the central region and having a second conductivity type, the first side being opposite to the second side, and the central region comprising a first diode junction, a second diode junction, and an intrinsic region that separates the first diode junction and the second diode junction along the longitudinal direction. 2. The apparatus of claim 1 , wherein the intrinsic region is an intrinsic silicon semiconductor region. 3. The apparatus of claim 1 , wherein the first lateral region and the second lateral region flank the central region along the first axis, wherein the intrinsic region is located between the first diode junction and the second diode junction along a second axis and third axis, and wherein the second axis is parallel to the longitudinal direction, the first axis is perpendicular to the second axis and the third axis, and the second axis is perpendicular to the third axis. 4. The apparatus of claim 3 , wherein the first lateral region comprises a first trench adjacent to the first side of the central region, and wherein the second lateral region comprises a second trench adjacent to the second side of the central region. 5. The apparatus of claim 1 , wherein the intrinsic region is a portion of the semiconductor substrate. 6. The apparatus of claim 5 , wherein the intrinsic region is formed by counter doping the portion of the semiconductor substrate with equal amounts of a first dopant having the first conductivity type and a second dopant having the second conductivity type. 7. The apparatus of claim 1 , wherein the first lateral region comprises an N-doped implant, wherein the second lateral region comprises a P-doped implant. 8. The apparatus of claim 1 , wherein the first lateral region comprises a P-doped implant, wherein the second lateral region comprises an N-doped implant. 9. A method comprising: implanting a first dopant of a first conductivity type into a first portion of the semiconductor substrate to form a first conductivity layer; implanting a second dopant of a second conductivity type into a second portion of the semiconductor substrate and at least a first portion of the first conductivity layer to form a second conductivity layer, wherein a portion of the second conductivity layer overlaps a second portion of the first conductivity layer to form at least two diode junctions; and forming an intrinsic region of the semiconductor substrate separating respective junction diodes of the at least two diode junctions along a longitudinal direction of an optical waveguide. 10. The method of claim 9 , further comprising: etching a first trench into the first conductivity layer; and etching a second trench into the second conductivity layer, wherein the at least two diode junctions and the intrinsic region are located between the first trench and the second trench. 11. The method of claim 10 , wherein the first trench and the second trench are aligned along a first axis, and the intrinsic region is aligned along a second axis, and wherein the second axis is parallel to the longitudinal direction, and the first axis is perpendicular to the second axis. 12. The method of claim 9 , wherein the intrinsic region is an intrinsic silicon semiconductor region. 13. The method of claim 9 , wherein the first dopant comprises an N-doped implant, wherein the second dopant comprises a P-doped implant. 14. The method of claim 9 , wherein the first dopant comprises a P-doped implant, wherein the second dopant comprises an N-doped implant. 15. An electro-optic modulator apparatus comprising: an optical waveguide extending along a longitudinal direction; a junction zone; a first diode junction comprising a first layer having a first conductive type and a second layer having a second conductive type, wherein the first diode junction is located on a semiconductor substrate and within the junction zone; a second diode junction comprising the first layer and the second layer, wherein the second diode junction is located on the semiconductor substrate and within the junction zone; and an intrinsic region located on the semiconductor substrate and separating the first diode junction and the second diode junction along the longitudinal direction. 16. The apparatus of claim 15 , wherein the intrinsic region is an intrinsic silicon semiconductor region. 17. The apparatus of claim 15 , further comprising a first terminal zone and a second terminal zone flanking the junction zone, wherein the first terminal zone comprises the first layer, and wherein the second terminal zone comprises the second layer. 18. The apparatus of claim 17 , further comprising a first trench extending into the first layer and a second trench extending into the second layer, wherein the first trench and the second trench flank opposite sides of the junction zone. 19. The apparatus of claim 18 , wherein the first layer comprises an N-doped implant, wherein the second layer comprises a P-doped implant. 20. The apparatus of claim 18 , wherein the first layer comprises a P-doped implant, wherein the second layer comprises an N-doped implant.

Assignees

Inventors

Classifications

  • G02F1/025Primary

    in an optical waveguide structure (G02F1/017, {G02F1/2257} take precedence) · CPC title

  • controlled by a high-frequency electromagnetic component in an electric waveguide structure · CPC title

  • in an optical wavequide structure · CPC title

  • semiconductor · CPC title

  • Physics · mapped topic

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10241354B1 cover?
Techniques regard electro-optic modulators are provided. For example, one or embodiments described herein can regard an apparatus that can comprise a first lateral region, a second lateral region, and a central region located on a semiconductor substrate. The first lateral region can be adjacent to a first side of the central region and can have a first conductivity type. The second lateral reg…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G02F1/025. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 26 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).