Vacuum sealed MEMS and CMOS package

Patent metadata

Field	Value
Publication number	US-9776856-B2
Application number	US-201314137672-A
Country	US
Kind code	B2
Filing date	Dec 20, 2013
Priority date	Dec 20, 2013
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A vacuum sealed MEMS and CMOS package and a process for making the same may include a capping wafer having a surface with a plurality of first cavities, a first device having a first surface with a second plurality of second cavities, a hermetic seal between the first surface of the first device and the surface of the capping wafer, and a second device having a first surface bonded to a second surface of the first device. The second device is a CMOS device with conductive through vias connecting the first device to a second surface of the second device, and conductive bumps on the second surface of the second device. Conductive bumps connect to the conductive through vias and wherein a plurality of conductive bumps connect to the second device. The hermetic seal forms a plurality of micro chambers between the capping wafer and the first device.

First claim

What is claimed is:

1. An apparatus, comprising:
a capping wafer having a surface with a plurality of first cavities formed therein;
a first device having a first surface with a plurality of second cavities formed therein;
a hermetic seal between the first surface of the first device and the surface of the capping wafer, wherein the hermetic seal forms a plurality of micro chambers between the capping wafer and the first device; and
a second device comprising:
an active device layer on a first surface of a substrate, wherein the active device layer comprises active devices;
a bonding layer on the active devices, wherein the active devices are interposed between the bonding layer and the substrate, wherein the bonding layer bonds the second device to a second surface of the first device;
a plurality of conductive through vias electrically connecting the first device and the active devices to a second surface of the substrate, wherein a first subset of the plurality of conductive through vias extend through the substrate, the active device layer, and at least a portion of the bonding layer, wherein a second subset of the plurality of conductive through vias extend through the substrate; and
a plurality of conductive bumps on the second surface of the substrate, wherein a first subset of the plurality of conductive bumps are electrically connected to the first device with the first subset of the plurality of conductive through vias, wherein a second subset of the plurality of conductive bumps are electrically connected to the active devices with the second subset of the plurality of conductive through vias.

2. The apparatus of claim 1 , wherein at least some of the plurality of second cavities include substrate material suspended by at least one edge.

3. The apparatus of claim 1 , wherein the active device layer is over the second subset of the plurality of conductive through vias.

4. The apparatus of claim 1 , wherein each of the plurality of micro chambers has an internal pressure of less than 100 mbar.

5. The apparatus of claim 1 , wherein the first device includes a gyroscope or an accelerometer exposed to one of the plurality of micro chambers, wherein the first subset of the plurality of conductive bumps are electrically connected to the gyroscope or accelerometer.

6. The apparatus of claim 1 , wherein the hermetic seal comprises a eutectic alloy material.

7. The apparatus of claim 6 , wherein the hermetic seal comprises a material selected from the group consisting of indium, gold, tin, copper, aluminum, germanium, and combinations thereof.

8. The apparatus of claim 1 , wherein the first device includes doped polysilicon conductors and a gyroscope or an accelerometer, wherein the doped polysilicon conductors couple the first subset of the plurality of conductive through vias to the gyroscope or accelerometer, wherein the first subset of the plurality of conductive through vias physically contact the doped polysilicon conductors.

9. An apparatus, comprising:
a MEMS device comprising:
a gyroscope or an accelerometer; and
a MEMS substrate having a first surface and a second surface opposite the first surface;

a capping wafer bonded to the first surface of the MEMS substrate;
a plurality of hermetically sealed micro chambers between the capping wafer and the MEMS device, the gyroscope or accelerometer being exposed to the plurality of hermetically sealed micro chambers, and the plurality of hermetically sealed micro chambers each having an internal pressure less than 1 bar; and
a CMOS device, a first surface of the CMOS device bonded to the MEMS device with a bonding layer such that the bonding layer is interposed between the CMOS device and the MEMS device, the CMOS device comprising:
an active device layer on a CMOS substrate;
one or more first conductive through vias connecting the active device layer to a second surface of the CMOS device, the one or more first conductive through vias extending through the CMOS substrate;
one or more second conductive through vias connecting the gyroscope or accelerometer to the second surface of the CMOS device, the one or more second conductive through vias extending through the active device layer, the bonding layer, and the CMOS substrate; and
a plurality of conductive bumps on the second surface of the CMOS device, the plurality of conductive bumps coupled to the one or more first conductive through vias and the one or more second conductive through vias.

10. The apparatus of claim 9 , wherein the plurality of hermetically sealed micro chambers has an internal pressure of less than 100 mbar.

11. The apparatus of claim 9 , wherein the plurality of hermetically sealed micro chambers include a suspended substrate structure.

12. The apparatus of claim 9 , wherein the MEMS device further includes an interconnect comprising doped polysilicon layers, and a gas diffusion barrier between the doped polysilicon layers.

13. The apparatus of claim 9 , wherein the one or more first conductive through vias and the one or more second conductive through vias are 10 to 20 conductive through vias.

14. A device comprising:
a first device comprising a plurality of conductive bumps on a first side and an active device layer on a second side, the active device layer electrically coupled to a first subset of the conductive bumps with first through vias extending into the first device;
a second device adhered to the first device with a bonding layer, the second device electrically coupled to a second subset of the conductive bumps with second through vias extending into the first device further than the first through vias, wherein the second through vias extend through the bonding layer and the active device layer, wherein the second device comprises a plurality of suspended substrate structures forming trenches; and
a capping wafer adhered to the second device with a hermetric seal, wherein the hermetric seal, the capping wafer, and the second device form a plurality of micro chambers, the micro chambers comprising cavities within the capping wafer and the trenches within the second device.

15. The device of claim 14 , wherein sidewalls of the suspended substrate structures comprise MEMS.

16. The device of claim 15 , wherein the MEMS include a gyroscope within one of the plurality of micro chambers.

17. The device of claim 14 , wherein the hermetric seal comprises a plurality of metal bonding layers forming a eutectic alloy compound.

18. The device of claim 17 , wherein the plurality of metal bonding layers comprise materials selected from the group consisting of indium, gold, tin, copper, aluminum, germanium, and combinations thereof.

19. The device of claim 14 , wherein each of the plurality of micro chambers forms a vacuum environment of less than 100 mbar.

20. The apparatus of claim 9 , wherein the a plurality of conductive bumps has a first subset and a second subset, the first subset coupled to the one or more first conductive through vias, the second subset coupled to the one or more second conductive through vias.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Chun-Wen
• Teng Yi-Chuan
• Tsai Hung-Chia
• Chu Chia-Hua

Classifications

• H10W20/216

  characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title