Method of manufacturing a semiconductor device with epitaxial layers and an alignment mark

Patent metadata

Field	Value
Publication number	US-10236258-B2
Application number	US-201615379533-A
Country	US
Kind code	B2
Filing date	Dec 15, 2016
Priority date	Dec 23, 2015
Publication date	Mar 19, 2019
Grant date	Mar 19, 2019

Abstract

An alignment mark in a process surface of a semiconductor layer includes a groove with a minimum width of at least 100 μm and a vertical extension in a range 100 nm to 1 μm. The alignment mark further includes at least one fin within the groove at a distance of at least 60 μm to a closest one of inner corners of the groove.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
(a) forming an initial alignment mark comprising a groove with a minimum width of at least 100 μm and a vertical extension in a range from 100 nm to 1 μm in a process surface of a semiconductor layer, and at least one fin formed within the groove at a distance of at least 60 μm to a closest inside corner of the groove;
(b) forming a device region by using a mask aligned to the initial alignment mark;
(c) increasing a thickness of the semiconductor layer by growing an epitaxial layer, wherein the initial alignment mark is imaged into the process surface;
(d) repeating (b) and (c) at least once;
(e) forming a substitutional alignment mark comprising a groove with a minimum width of at least 100 μm and a vertical extension in a range from 100 nm to 1 μm in the process surface, and at least one fin formed within the groove at a distance of at least 60 μm to a closest inside corner of the groove; and
(f) repeating (b) and (c) at least once, wherein the respective mask is aligned to the substitutional alignment mark.

2. The method of claim 1 , wherein
forming the device region comprises implanting dopants through openings of the respective mask.

3. The method of claim 1 , further comprising:
forming, after (f), a further substitutional alignment mark comprising a groove with a minimum width of at least 100 μm and a vertical extension in a range from 100 nm to 1 μm in the process surface, and at least one fin formed within the groove at a distance of at least 60 μm to the closest inside corner of the groove.

4. The method of claim 3 , further comprising:
repeating (b) and (c) at least once, wherein the respective mask is aligned to the substitutional alignment mark imaged into the process surface.

5. The method of claim 1 , further comprising:
forming transistor cells in the semiconductor layer, wherein implant and etch masks for forming the transistor cells are aligned to the substitutional or to the further substitutional alignment mark imaged into the process surface.

6. The method of claim 1 , wherein
the process surface is a <001> crystal plane and sidewalls of the at least one fin are <110> crystal planes.

7. The method of claim 1 , wherein
sidewalls of the at least one fin extend along <110> crystal directions.

8. The method of claim 1 , wherein
a length of the at least one fin is in a range from 5 μm to 50 μm.

9. The method of claim 1 , wherein
a width of the at least one fin is in a range from 3 μm to 10 μm.

10. The method of claim 1 , wherein
the epitaxial layers have a thickness in a range from 3 μm to 7 μm.

11. The method of claim 1 , wherein
a minimum distance between the at least one fin and a sidewall of the groove closest to the at least one fin is at least 25 μm.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Moser Andreas
• Weber Hans
• Treu Michael
• Baumgartl Johannes
• Mezoesi Gabor

Classifications

• G03F9/7076

  Mark details, e.g. phase grating mark, temporary mark · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P30/22

  using masks · CPC title

• H10W46/503

  Located in scribe lines · CPC title

• H10W46/301

  for alignment · CPC title