System on chip (SoC), mobile electronic device including the same, and method of operating the SoC

Patent metadata

Field	Value
Publication number	US-10229079-B2
Application number	US-201815989539-A
Country	US
Kind code	B2
Filing date	May 25, 2018
Priority date	Dec 9, 2014
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

A system on chip (SoC) is present that includes a plurality of master interfaces, a plurality of slave interfaces, and an interface circuit which is connected between the plurality of master interfaces and the plurality of slave interfaces and includes a plurality of components. When a first master interface among the plurality of master interfaces and a first slave interface among the plurality of slave interfaces are paired, a first group of the components which forms a first signal path between the first master interface and the first slave interface among the plurality of components is enabled according to a control of the first master interface.

First claim

What is claimed is:

1. A system on chip (SoC) comprising:
a plurality of master interfaces including a first master interface and a second master interface;
a plurality of slave interfaces including a first slave interface and a second slave interface; and
an interface circuit connected between the plurality of master interfaces and the plurality of slave interfaces and including a plurality of components, the plurality of components including a first group of components and a second group of components,
wherein the first group of components are configured to be enabled based on a control of the first master interface to form a first signal path between the first master interface and the first slave interface,
wherein the second group of components are configured to be enabled based on the control of the first master interface to form a second signal path between the first master interface and the second slave interface, and
wherein the first group of components and the second group of components share at least one component.

2. The SoC of claim 1 , wherein the first group of components include at least one component that is not shared by the second group of components.

3. The SoC of claim 1 , wherein, among the first group of components, one or more components that are not shared by the second signal path are configured to be disabled before the second signal path is formed based on the control of the first master interface.

4. The SoC of claim 1 , wherein each of the plurality of components is an M-to-1 switch, a 1-to-N switch, a multiplexor, a de-multiplexor, or a bridge, each of M and N being an integer greater than one.

5. The SoC of claim 1 , wherein a first request is transmitted from the first master interface to the first slave interface through the first signal path.

6. The SoC of claim 5 , wherein the first slave interface transmits a first response to the first master interface through the first signal path in response to the first request.

7. The SoC of claim 6 , wherein the first group of components are disabled based on the control of the first master interface after the first response is transmitted to the first master interface.

8. A system on chip (SoC) comprising:
a plurality of master interfaces including a first master interface and a second master interface;
a plurality of slave interfaces including a first slave interface and a second slave interface; and
a plurality of components connected between the plurality of master interfaces and the plurality of slave interfaces, and including a first group of components and a second group of components,
wherein the first group of components are configured to be enabled based on a control of the first master interface to form a first signal path between the first master interface and the first slave interface, or configured to be enabled based on a control of the second master interface to form a second signal path between the second master interface and the first slave interface,
the second group of components are configured to be enabled based on the control of the first master interface to form a third signal path between the first master interface and the second slave interface, or configured to be enabled based on the control of the second master interface to form a fourth signal path between the second master interface and the second slave interface, and
the first group of components and the second group of components share at least one component.

9. The SoC of claim 8 , wherein the first group of components include at least one component that is not shared by the second group of components.

10. The SoC of claim 8 , wherein, among the first group of components, one or more components that are not shared by the second signal path are configured to be disabled before the second signal path is formed.

11. The SoC of claim 8 , wherein, among the second group of components, components that are not shared by the first signal path are disabled when the first group of components are enabled to form the first signal path.

12. The SoC of claim 8 , wherein, when a first request is transmitted from the first master interface to the first slave interface, the first master interface enables only the first group of components.

13. The SoC of claim 8 , wherein each of the plurality of components is an M-to-1 switch, a 1-to-N switch, a multiplexor, a de-multiplexor, or a bridge, each of M and N being an integer greater than one.

14. A system on chip (SoC) comprising:
a plurality of master interfaces including a first master interface and a second master interface;
a plurality of slave interfaces including a first slave interface, a second slave interface, a third slave interface and a fourth slave interface; and
a plurality of components connected between the plurality of master interfaces and the plurality of slave interfaces, and including a first group of components, a second group of components, a third group of components and a fourth group of components,
wherein the first group of components are configured to be enabled based on a control of the first master interface to form a first signal path between the first master interface and the first slave interface,
the second group of components are configured to be enabled based on the control of the first master interface to form a second signal path between the first master interface and the second slave interface,
the third group of components are configured to be enabled based on a control of the second master interface to form a third signal path between the second master interface and the third slave interface,
the fourth group of components are configured to be enabled based on the contro of the second master interface to form a fourth signal path between the second master interface and the fourth slave interface,
the first group of components and the second group of components share at leas one component, and
the third group of components and the fourth group of components share at least one component.

15. The SoC of claim 14 , wherein the first group of components include at least one component that is not shared by the second group of components.

16. The SoC of claim 14 , wherein the first group of components include at least one component that is not shared by the third group of components.

17. The SoC of claim 14 , wherein the first group of components and the third group of components do not share any component.

18. The SoC of claim 14 , wherein the first group of components and the third group of components share at least one component.

19. The SoC of claim 14 , wherein, among the first group of components, one or more components that are not shared by the third signal path are configured to be disabled before the third signal path is formed.

20. The SoC of claim 14 , wherein, among the second, third and fourth groups of components, components that are not shared by the first signal path are disabled, when the first group of components are enabled to form the first signal path.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoo Jun Hee
• Yun Jae Geun
• Jeong Bub Chul
• Kang Dong Soo
• Lee Kyeo Rae
• Jo Seong Min

Classifications

• G06F13/1621

  by maintaining request order · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/368 Primary

  with decentralised access control · CPC title

• G06F13/00 Primary

  Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor  G06F9/46}; multiprocessor systems  G06F15/16 ) · CPC title

• Y02D10/14

  Cross-Sectional Technologies · mapped topic