System on chip for enhancing quality of service and method of controlling the same

US9367499B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9367499-B2
Application numberUS-201313790104-A
CountryUS
Kind codeB2
Filing dateMar 8, 2013
Priority dateApr 4, 2012
Publication dateJun 14, 2016
Grant dateJun 14, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A system on chip (SOC) include at least one slave device, a plurality of master devices, a plurality of service controllers and an interconnect device. The master devices generate requests to demand services from the slave device, respectively. The service controllers generate urgent information signals and priority information signals for each of the master devices. The interconnect device is coupled to the slave device and the master devices through respective channels. The interconnect device performs an arbitrating operation on the requests based on the priority information signals and controls request flows between the slave device and the master devices based on the urgent information signals.

First claim

Opening claim text (preview).

What is claimed is: 1. A system on chip (SOC) comprising: at least one slave device: a plurality of master devices configured to generate requests to demand services from the slave device, respectively; a plurality of service controllers configured to generate urgent information signals and priority information signals for each of the respective master devices; and an interconnect device coupled to the slave device and the master devices through respective channels, the interconnect device configured to perform an arbitrating operation on the requests based on the priority information signals and configured to control request flows between the slave device and the master devices based on the urgent information signals, wherein the control of the request flows comprises blocking one of the request flows by masking at least one signal involved in a corresponding handshaking scheme, wherein the interconnect device includes a limit signal generator configured to generate a limit signal based on at least one of the urgent information signals, wherein at least one of the service controllers includes a limiter configured to block the one request flow between the corresponding master device and the interconnect device based on the limit signal, wherein the limiter comprises: a synchronizer configured to generate a synchronized limit signal based on the limit signal from the interconnect device; and a mask unit configured to block the one request flow between the corresponding master device and the interconnect device based on the synchronized limit signal. 2. The SOC of claim 1 , wherein the limit signal generator is configured to generate the limit signal based on the urgent information signals that are generated by the service controllers except the service controller receiving the limit signal. 3. The SOC of claim 1 , wherein the synchronizer is configured to sample the limit signal in response to falling edges of a global clock signal of the interconnect device to generate the synchronized limit signal. 4. The SOC of claim 1 , wherein the mask unit comprises: a first logic gate configured to output a masked valid signal by performing a logic operation on the synchronized limit signal and a valid signal from the corresponding master device; and a second logic gate configured to output a masked ready signal by performing a logic operation on the synchronized limit signal and a ready signal from the interconnect device. 5. A method of controlling a system on chip (SOC) comprising at least one slave device, a plurality of master devices, a plurality of service controllers and an interconnect device, the slave device and the master devices coupled to the interconnect device through respective channels, the master devices generating requests to demand services from the slave device, respectively, the method comprising: detecting at least one of bandwidths and latencies of the master devices based on operational characteristics of the master devices; generating, urgent information signals and priority information signals based on at least one of the bandwidths and the latencies; performing an arbitrating operation on the requests based on the priority information signals; and controlling request flows between the slave device and the master devices based on the urgent information signals, wherein the controlling comprises blocking one of the request flows by masking at least one signal involved in a corresponding handshaking scheme, and wherein the controlling further comprises: generating, by the interconnect device, a limit signal based on at least one of the urgent information signals; and blocking, by a limiter of one of the service controllers, the one request flow between the corresponding master device and the interconnect device based on the limit signal, wherein the limiter comprises: a synchronizer configured to generate a synchronized limit signal based on the limit signal from the interconnect device; and a mask unit configured to block the one request flow between the corresponding master device and the interconnect device based on the synchronized limit signal. 6. The method of claim 5 , wherein the requests are transferred according to the handshake scheme that uses a valid signal and a ready signal, and wherein controlling the request flows between the slave device and the master devices includes deactivating at least one of the valid signal and the ready signal based on the urgent information signals. 7. A system on chip (SOC) comprising: at least one slave device: a plurality of master devices configured to generate requests to demand services from the slave device, respectively; a plurality of service controllers configured to generate urgent information signals and priority information signals for each of the respective master devices; and an interconnect device coupled to the slave device and the master devices through respective channels, the interconnect device configured to perform an arbitrating operation on the requests based on the priority information signals and configured to control request flows between the slave device and the master devices based on the urgent information signals, wherein the interconnect device includes a limit signal generator configured to generate a limit signal based on at least one of the urgent information signals, wherein at least one of the service controllers includes a limiter configured to block the request flow between the corresponding master device and the interconnect device based on the limit signal, and wherein the limiter comprises a synchronizer configured to generate a synchronized limit signal based on the limit signal from the interconnect device and a mask unit configured to block the request flow between the corresponding master device and the interconnect device based on the synchronized limit signal.

Assignees

Inventors

Classifications

  • using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

  • G06F13/364Primary

    using independent requests or grants, e.g. using separated request and grant lines · CPC title

  • Package configurations · CPC title

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Frequently asked questions

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What does patent US9367499B2 cover?
A system on chip (SOC) include at least one slave device, a plurality of master devices, a plurality of service controllers and an interconnect device. The master devices generate requests to demand services from the slave device, respectively. The service controllers generate urgent information signals and priority information signals for each of the master devices. The interconnect device is …
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F13/364. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 14 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).