Configurable input range for continuous-time sigma delta modulators

Patent metadata

Field	Value
Publication number	US-10224951-B2
Application number	US-201615276561-A
Country	US
Kind code	B2
Filing date	Sep 26, 2016
Priority date	Jan 8, 2016
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

A continuous-time sigma delta modulator circuit includes a scaling circuit that scales an input analog signal by a selectable range of different scaling factors in order to change a range of signal levels of the input analog signal to a desired range of signal levels in a scaled analog signal prior to conversion of the scaled analog signal to a digital signal. The scaling factor is selected based on the range of signal levels of the input analog signal in order to provide signal levels of the scaled signal within a desired range. The scaling circuit maintains current flow of the input analog signal at a substantially constant level regardless of the different scaling factors that are used to scale the input analog signal.

First claim

What is claimed is:

1. A continuous-time sigma delta modulator (CTSDM) circuit to scale an input signal to be within a predetermined desired range of values, the CTSDM circuit comprising:
a scaling circuit to adjust a signal range of an input analog signal according to a shared selectable scaling factor and output a range-adjusted analog signal; and
an impedance network to maintain a substantially constant current flow of the input analog signal by communicating the shared scaling factor to an amplifier circuit.

2. The CTSDM circuit of claim 1 , further comprising:
an integrating amplifier circuit to amplify the range-adjusted analog signal and output an amplified analog signal;
a quantizer circuit to convert the amplified analog signal to a digital signal; and
a digital to analog converter (DAC) circuit to convert the digital signal output from the quantizer circuit to an intermediate analog signal to be summed with the range-adjusted analog signal at an input to the integrating amplifier circuit.

3. The CTSDM circuit of claim 2 , wherein the impedance network comprises a first resistance element and a first switch disposed in series, a state of the first switch being changeable according to the selectable scaling factor.

4. The CTSDM circuit of claim 3 , wherein the impedance network further comprises a second switch disposed between a junction of the first resistance element and the first switch on a first side of the second switch, and ground on a second side of the second switch, a state of the second switch being changeable according to the selectable scaling factor.

5. The CTSDM circuit of claim 4 , wherein the scaling circuit is configured to close the second switch when opening the first switch and open the second switch when closing the first switch.

6. The CTSDM circuit of claim 4 , wherein the impedance network further comprises a second resistance element and a third switch disposed in series and collectively in parallel with the first resistance element and the first switch, a state of the third switch being changeable according to the selectable scaling factor.

7. The CTSDM circuit of claim 1 , wherein
the input analog signal, range-adjusted analog signal, and amplified analog signal are differential signals;
the integrating amplifier circuit has a first amplifier input and a second amplifier input to receive the range-adjusted analog signal, and has a first amplifier output and a second amplifier output to output the amplified analog signal;
the quantizer circuit has a first quantizer input coupled with the first amplifier output and a second quantizer input coupled with the second amplifier output to receive the amplified analog signal;
the DAC circuit has a first analog output coupled with the first amplifier input at a first summing node and a second analog output coupled with the second amplifier input at a second summing node;
the impedance network comprises:
a first resistance element and a first switch disposed in series between a first analog signal input and the first summing node;
a second resistance element and a second switch disposed in series between a second analog signal input and the second summing node; and
a third switch disposed between a junction of the first resistance element and the first switch on a first side of the third switch, and between a junction of the second resistance element and the second switch on a second side of the third switch; and
wherein a state of each of the first switch, the second switch, and the third switch is changeable according to the selectable scaling factor.

8. The CTSDM circuit of claim 7 , wherein the scaling circuit is configured to close the third switch when opening the first switch and the second switch, and open the third switch when closing the first switch and the second switch.

9. The CTSDM circuit of claim 7 , wherein the impedance network further comprises:
a third resistance element and a fourth switch disposed in series between the first analog signal input and the first summing node and in parallel with the first resistance element and the first switch; and
a fourth resistance element and a fifth switch disposed in series between the second analog signal input and the second summing node and in parallel with the second resistance element and the second switch;
wherein a state of the fourth switch and a state of the fifth switch are changeable according to the selectable scaling factor.

10. The CTSDM circuit of claim 9 , wherein the scaling circuit is configured to close the fourth switch when closing the fifth switch and open the fourth switch when opening the fifth switch.

11. The CTSDM circuit of claim 7 , wherein the scaling circuit is configured to close the second switch when closing the first switch and open the second switch when opening the first switch.

12. The CTSDM circuit of claim 7 , further comprising a first integrator capacitor coupled between the first amplifier input and the first amplifier output, and a second integrator capacitor coupled between the second amplifier input and the second amplifier output.

13. The CTSDM circuit of claim 1 , wherein
the input analog signal, range-adjusted analog signal, and amplified analog signal are differential signals;
the integrating amplifier circuit has a first amplifier input and a second amplifier input to receive the range-adjusted analog signal and a first amplifier output and a second amplifier output to output the amplified analog signal;
the quantizer circuit has a first quantizer input coupled with the first amplifier output and a second quantizer input coupled with the second amplifier output to receive the amplified analog signal;
the DAC circuit has a first analog output coupled with the first amplifier input at a first summing node and a second analog output coupled with the second amplifier input at a second summing node;
the impedance network comprises:
a first resistance element and a first switch disposed in series between a first analog signal input and the first summing node;
a second resistance element and a second switch disposed in series between a second analog signal input and the second summing node;
a third switch disposed between a junction of the first resistance element and the first switch on a first side of the third switch, and the second summing node on a second side of the third switch; and
a fourth switch disposed between a junction of the second resistance element and the second switch on a first side of the fourth switch, and the first summing node on a second side of the fourth switch; and
wherein a state of each of the first switch, the second switch, the third switch, and the fourth switch is changeable according to the selectable scaling factor.

14. The CTSDM circuit of claim 13 , wherein the scaling circuit is configured to close the third switch and fourth switches when opening the first and second switches, and open the third and fourth switches when closing the first and second switches.

15. A method of scaling an input signal to an integrating amplifier to be within a predetermined desired range of values, the method comprising:
selectively establishing a scaling factor of a shared scaling circuit to adjust a signal range of an input analog signal;
adjusting the signal range of the input analog signal by the scaling circuit according to the scaling factor to output a range-adjusted analog signal;
reconfiguring an impedance network of the scaling circuit to maintain a substantially constant current flow of the input analog signal across two or more selectable scaling factors by communicating the sha

Assignees

• Analog Devices Global

Inventors

• Nittala Venkata Aruna Srikanth
• Gutta Avinash

Classifications

• H03M3/486 Primary

  by adapting the input gain · CPC title

• H03M3/322 Primary

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, e.g. by using stored correction values, H03M3/378) · CPC title

• H03M3/30

  Delta-sigma modulation · CPC title

• H03M3/43

  the quantiser being a single bit one · CPC title

• H03M1/1009

  Calibration · CPC title