Electrostatic discharge power clamp with fail-safe design

Patent metadata

Field	Value
Publication number	US-9882376-B2
Application number	US-201414577145-A
Country	US
Kind code	B2
Filing date	Dec 19, 2014
Priority date	Dec 19, 2014
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

Electrostatic discharge protection circuits and methods of fabricating an electrostatic discharge protection circuit, as well as methods of protecting an integrated circuit from a transient electrostatic discharge event. The electrostatic discharge protection circuit includes a power clamp device, a first timing circuit with a first resistor and a first capacitor that is coupled with the first resistor at a first node, and a second timing circuit including a second resistor and a second capacitor that is coupled with the second resistor at a second node. The electrostatic discharge protection circuit further includes a logic gate with a first input coupled with the first node, a second input coupled with the second node, and an output coupled with the power clamp device. The logic gate responds to voltages at the first and second nodes to control the impedance state of the power clamp device.

First claim

What is claimed is:

1. An electrostatic discharge protection circuit comprising:
a power clamp device;
a first timing circuit including a first resistor and a first capacitor that is coupled with the first resistor at a first node;
a second timing circuit including a second resistor and a second capacitor that is coupled with the second resistor at a second node; and
a logic gate including a first input coupled with the first node, a second input coupled with the second node, and an output coupled with the power clamp device,

wherein the first capacitor and the second capacitor each comprise at least one deep trench capacitor.

2. The electrostatic discharge protection circuit of claim 1 , wherein the first timing circuit is coupled in series between a positive rail of a power supply and a negative rail of the power supply, and the second timing circuit is coupled in series between the positive rail of the power supply and the negative rail of the power supply.

3. The electrostatic discharge protection circuit of claim 1 , wherein the logic gate is a NOR gate.

4. The electrostatic discharge protection circuit of claim 1 , wherein the logic gate is a NAND gate, and further comprising:
a first inverter coupling the first node with the first input to the NAND gate; and
a second inverter coupling the second node with the second input to the NAND gate.

5. The electrostatic discharge protection circuit of claim 1 , wherein the power clamp device is a field-effect transistor including a gate with a width greater than one thousand microns.

6. The electrostatic discharge protection circuit of claim 1 , further comprising:
one or more inverters arranged to couple the logic gate with the power clamp device.

7. The electrostatic discharge protection circuit of claim 1 , wherein the first resistor and the second resistor have equal electrical resistances, the first capacitor and the second capacitor have equal capacitances, and the first timing circuit and the second timing circuit have equal time constants.

8. A method of fabricating an electrostatic discharge protection circuit for a chip, the method comprising:
forming, using a substrate, a first resistor and a first capacitor of a first timing circuit;
forming, using the substrate, a second resistor and a second capacitor of a second timing circuit;
forming, using the substrate, a power clamp device; and
forming, using the substrate, a logic gate including a first input coupled with a first node coupling the first capacitor with the first resistor, a second input coupled with a second node between the second capacitor and the second resistor, and an output coupled with the power clamp device,

wherein the first capacitor and the second capacitor each comprise at least one deep trench capacitor.

9. The method of claim 8 , wherein the first capacitor is formed using a first deep trench defined in the substrate and the second capacitor is formed using a second deep trench defined in the substrate.

10. The method of claim 8 , further comprising:
coupling the first timing circuit in series between a positive rail of a power supply and a negative rail of the power supply; and
coupling the second timing circuit in series between the positive rail of the power supply and the negative rail of the power supply.

11. The method of claim 8 , wherein the logic gate is a NOR gate.

12. The method of claim 8 , wherein the logic gate is a NAND gate, and further comprising:
forming, using the substrate, a first inverter coupling the first node with the first input to the NAND gate; and
forming, using the substrate, a second inverter coupling the second node with the second input to the NAND gate.

13. A method of operating an electrostatic discharge protection circuit when power is applied to a chip and the electrostatic discharge protection circuit on the chip, the method comprising:
supplying a first voltage to a first input of a logic gate from a first node between a first resistor and a first capacitor of a first timing circuit;
supplying a second voltage to a second input of the logic gate from a second node between a second resistor and a second capacitor of a second timing circuit; and
outputting a third voltage from the logic gate to a power clamp device based on the first voltage and the second voltage,
wherein the third voltage places the power clamp device in a high-impedance state, and the first capacitor and the second capacitor are each deep trench capacitors.

14. The method of claim 13 , wherein the first capacitor is a non-defective deep trench capacitor, the second capacitor is a defective deep trench capacitor, the first voltage is equal to a power supply voltage, and the second voltage is equal to ground.

15. The method of claim 13 , wherein the logic gate is a NOR gate, and outputting the third voltage from the NOR gate to the power clamp device based on the first voltage and the second voltage comprises:
determining an output from the NOR gate by applying a logical NOR truth table to the first voltage and the second voltage.

16. The method of claim 13 , wherein the logic gate is a NAND gate, and outputting the third voltage from the NAND gate to the power clamp device based on the first voltage and the second voltage comprises:
inverting the first voltage before the first voltage is supplied to the first input of the logic gate;
inverting the second voltage before the second voltage is supplied to the second input of the logic gate;
determining an output from the NAND gate by applying a logical conjunction truth table to the inverted first voltage and the inverted second voltage.

17. The method of claim 13 , wherein the first resistor and the second resistor have equal electrical resistances, the first capacitor and the second capacitor have equal capacitances, and the first timing circuit and the second timing circuit have equal time constants.

18. An electrostatic discharge protection circuit comprising:
a power clamp device;
a timing circuit including a resistor, a first capacitor that is coupled with the resistor at a node, and a second capacitor that is coupled with the resistor at the node;
a first field-effect transistor including a first gate, the first field-effect transistor coupled in series with the first capacitor between a positive rail of a power supply and a negative rail of the power supply; and
a decoder including a first output line coupled with the first gate, the decoder configured to selectively output a first voltage on the first output line to the first gate.

19. The electrostatic discharge protection circuit of claim 18 , further comprising:
a second field-effect transistor including a second gate, the second field-effect transistor coupled in series with the second capacitor between the positive rail of the power supply and the negative rail of the power supply,
wherein the decoder includes a second output line coupled with the second gate, the decoder configured selectively output a second voltage on the second output line to the second gate.

Assignees

• IBM

Inventors

• Fifield John A
• Gauthier Jr Robert J
• Li Junjun

Classifications

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H01L29/945

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H01L23/5228

  Electricity · mapped topic