Superjunction semiconductor device having a superstructure

Patent metadata

Field	Value
Publication number	US-10224394-B2
Application number	US-201815887660-A
Country	US
Kind code	B2
Filing date	Feb 2, 2018
Priority date	Nov 26, 2015
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

According to an embodiment of a semiconductor substrate, the semiconductor substrate includes a superjunction structure in a device region of a semiconductor layer and an alignment mark in a kerf region of the semiconductor layer. The superjunction structure includes first regions and second regions of opposite conductivity types, the first and the second regions alternating along at least one horizontal direction. The alignment mark includes a vertical step formed by an alignment structure projecting or recessed from a main surface of the semiconductor layer. The alignment structure is of a material of the first regions of the superjunction structure.

First claim

What is claimed is:

1. A semiconductor substrate, comprising:
a superjunction structure in a device region of a semiconductor layer, the superjunction structure comprising first regions and second regions of opposite conductivity types, the first and the second regions alternating along at least one horizontal direction; and
an alignment mark in a kerf region of the semiconductor layer, the alignment mark comprising a vertical step formed by an alignment structure projecting or recessed from a main surface of the semiconductor layer,
wherein the alignment structure comprises a material of the first regions of the superjunction structure.

2. The semiconductor substrate of claim 1 , wherein a vertical extension of the alignment structure is equal to a vertical extension of the first regions.

3. The semiconductor substrate of claim 1 , wherein the alignment structure comprises separated stripe-shaped portions.

4. The semiconductor substrate of claim 1 , wherein a vertical extension of the vertical step is at least 50 nm.

5. The semiconductor substrate of claim 1 , wherein a vertical extension of the vertical step is in a range from 50 nm to 2 μm.

6. The semiconductor substrate of claim 1 , wherein a vertical extension of the vertical step is in a range from 100 nm to 500 nm.

7. The semiconductor substrate of claim 1 , wherein the first regions are disposed in first trenches formed in the semiconductor layer, and wherein the second regions are disposed in mesa portions of the semiconductor layer between the first trenches.

8. The semiconductor substrate of claim 1 , wherein the first and the second regions comprise an insulating material.

9. The semiconductor substrate of claim 1 , wherein the first and the second regions comprise a semiconducting material.

10. The semiconductor substrate of claim 1 , wherein the first and the second regions comprise a highly-conductive material.

11. The semiconductor substrate of claim 1 , wherein dopant concentrations in and dimensions of the first and the second regions are selected such that charge carriers in the superjunction structure approximately compensate each other and the superjunction structure fully depletes at voltages below a maximum blocking voltage of a semiconductor device included in the semiconductor substrate.

12. The semiconductor substrate of claim 1 , wherein interfaces between the first and the second regions in a device region of the semiconductor substrate form compensation pn junctions.

13. The semiconductor substrate of claim 1 , further comprising an epitaxial layer formed on the main surface of the semiconductor layer over the device region and the kerf region, wherein the epitaxial layer images the alignment mark on an epitaxy surface of the epitaxial layer facing away from the semiconductor layer.

14. The semiconductor substrate of claim 13 , further comprising a conformal gate dielectric layer formed on the epitaxy surface of the epitaxial layer facing away from the semiconductor layer, wherein the conformal gate dielectric layer images the alignment mark on a surface of the conformal gate dielectric layer facing away from the epitaxial layer.

15. The semiconductor substrate of claim 14 , further comprising a conductive layer formed on the conformal gate dielectric layer.

16. The semiconductor substrate of claim 1 , wherein the alignment structure is recessed below the main surface of the semiconductor layer, and wherein the vertical step is between the recessed alignment structure and a surrounding portion of the semiconductor layer.

17. The semiconductor substrate of claim 1 , further comprising a gate trench in the semiconductor layer.

18. A semiconductor device, comprising:
a superjunction structure in an active region of a semiconductor portion, the superjunction structure comprising first regions and second regions of opposite conductivity types, the first and the second regions alternating along at least one horizontal direction; and
an alignment mark in an inactive region of the semiconductor portion, the alignment mark comprising a vertical step formed by an alignment structure projecting or recessed from a first surface of the semiconductor portion,
wherein the alignment structure comprises a material of the first regions of the superjunction structure.

19. The semiconductor device of claim 18 , wherein a vertical extension of the alignment structure is equal to a vertical extension of the first regions.

20. The semiconductor device of claim 18 , wherein a vertical extension of the step is at least 50 nm.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Weber Hans
• Fachmann Christian
• Tutuc Daniel
• Voerckel Andreas

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10W46/503

  Located in scribe lines · CPC title