Semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-10224339-B2
Application number	US-201715822586-A
Country	US
Kind code	B2
Filing date	Nov 27, 2017
Priority date	Mar 2, 2016
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral circuit gate pattern on a first substrate, an impurity region in the first substrate and spaced apart from the peripheral circuit gate pattern, a cell array structure on the peripheral circuit gate pattern, a second substrate between the peripheral circuit gate pattern and the cell array structure, and a via that is in contact with the impurity region and disposed between the first substrate and the second substrate. The via electrically connects the first and second substrates to each other.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a peripheral circuit gate pattern on a first substrate;
a cell array structure on the peripheral circuit gate pattern;
a second substrate between the first substrate and the cell array structure; and
a via disposed between the first substrate and the second substrate and spaced apart from the peripheral circuit gate pattern,
wherein the via electrically connects the first and second substrates to each other.

2. The semiconductor memory device of claim 1 , further comprising an impurity region in the first substrate and spaced apart from the peripheral circuit gate pattern,
wherein the impurity region has a conductivity different from that of the first substrate and receives an end of the via.

3. The semiconductor memory device of claim 2 , wherein the impurity region comprises a first impurity region and a second impurity region enveloping the first impurity region,
wherein the first impurity region has an impurity concentration greater than that of the second impurity region.

4. The semiconductor memory device of claim 1 , further comprising:
a source/drain region on a side of the peripheral circuit gate pattern in the first substrate; and
a contact plug that is in contact with the source/drain region and disposed between the first substrate and the second substrate,
wherein the via includes a top surface coplanar with a bottom surface of the second substrate, and
wherein the contact plug includes a top surface lower than the bottom surface of the second substrate relative to the first substrate.

5. The semiconductor memory device of claim 1 , wherein
the first substrate comprises a peripheral circuit region and a ground region in the peripheral circuit region,
the second substrate comprises a cell array region vertically overlapping the peripheral circuit region, and
the via is disposed between the cell array region and the ground region.

6. The semiconductor memory device of claim 1 , wherein
the first substrate comprises a peripheral circuit region disposed on a portion of a central part of the first, substrate and a ground region disposed on a portion of a circumferential part of the first substrate,
the second substrate comprises a cell array region vertically overlapping the peripheral circuit region and a contact region vertically overlapping the ground region, and
the via is disposed between the contact region and the ground region.

7. The semiconductor memory device of claim 6 , wherein
the via comprises a first sidewall and a second sidewall facing each other,
the second substrate comprises a first side surface and a second side surface facing each other,
wherein the second sidewall of the via is coplanar with the second side surface of the second substrate, and the first sidewall of the via is disposed between the first and second side surfaces of the second substrate.

8. The semiconductor memory device of claim 7 , further comprising an isolation pattern that is in contact with the second sidewall of the via and wraps the second side surface of the second substrate,
wherein the isolation pattern has a thickness substantially equal to a sum of a thickness of the via and a thickness of the second substrate.

9. The semiconductor memory device of claim 1 , further comprising an isolation pattern wrapping a side surface of the second substrate.

10. The semiconductor memory device of claim 9 , wherein the first substrate has a planar area substantially equal to a sum of a planar area of the second substrate and a planar area of the isolation pattern.

11. The semiconductor memory device of claim 9 , wherein the isolation pattern has a thickness greater than that of the second substrate.

12. The semiconductor memory device of claim 1 , wherein the cell array structure comprises:
a stack structure including gate patterns that are stacked on the second substrate;
a vertical channel region penetrating the stack structure; and
a charge storage structure between the vertical channel region and each of the gate patterns.

Assignees

• Zhang Gang
• Kim Hyuk
• Kwon Yong Hyun
• Park Sangwuk
• Samsung Electronics Co Ltd

Inventors

• Zhang Gang
• Kim Hyuk
• Kwon Yong-Hyun
• Park Sangwuk

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L27/11573 Primary

  Electricity · mapped topic

• H01L27/1207

  Electricity · mapped topic

• H01L2924/1438

  Electricity · mapped topic

• H01L27/0925

  Electricity · mapped topic