Semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-9490263-B2
Application number	US-201414312702-A
Country	US
Kind code	B2
Filing date	Jun 24, 2014
Priority date	Sep 24, 2013
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A semiconductor device includes a substrate on which a plurality of logic cells are provided, and a plurality of active portions provided on the substrate and extending in a first direction. Contacts and gate structures extend in a second direction intersecting the first direction and are alternately arranged. A common conductive line extends along a boundary region of the plurality of logic cells in the first direction. At least one of the contacts is electrically connected to the common conductive line through a via therebetween, and each of the contacts intersects a plurality of the active portions. End portions of the contacts are aligned with each other along the first direction.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate on which a plurality of logic cells are provided;
a plurality of active portions provided on the substrate and extending in a first direction;
contacts and gate structures extending in a second direction intersecting the first direction, the contacts and the gate structures alternately arranged;
a common conductive line extending along a boundary region of the plurality of logic cells in the first direction,
wherein at least one of the contacts is electrically connected to the common conductive line through a via therebetween,
wherein each of the contacts intersects a plurality of the active portions,
wherein end portions of the contacts are aligned with each other along the first direction,
wherein each of the logic cells includes a P-type metal-oxide-semiconductor field effect transistor (PMOSFET) region and an N-type metal-oxide-semiconductor field effect transistor (NMOSFET) region,
wherein the contacts include PMOS contacts on the PMOSFET region and NMOS contacts on the NMOSFET region, and
wherein the PMOS contacts and the NMOS contacts are seperated from each other at a boundary region of the PMOSFET region and the NMOSFET region; and
a first device isolation layer provided in the substrate between the PMOSFET region and the NMOSFET region, and
wherein end portions of the PMOS contacts or the NMOS contacts are aligned with each other in the first direction on the first device isolation layer.

2. The semiconductor device of claim 1 , wherein each of the contacts is in contact with the plurality of active portions.

3. The semiconductor device of claim 1 , wherein each of the plurality of active portions includes source/drain regions, and
wherein each of the contacts is connected in common to a plurality of source/drain regions adjacent to each other in the second direction.

4. The semiconductor device of claim 1 , wherein each PMOS contact is aligned with a respective NMOS contact in the second direction.

5. The semiconductor device of claim 1 , further comprising:
a first separating insulation layer extending in the first direction on the boundary region of the PMOSFET region and the NMOSFET region,
wherein the first separating insulation layer separates the PMOS contacts from the NMOS contacts.

6. The semiconductor device of claim 1 , wherein the plurality of logic cells comprises: a first logic cell; and a second logic cell spaced apart from the first logic cell, and the common conductive line is disposed between the first logic cell and the second logic cell,
the semiconductor device, further comprising:
a second device isolation layer provided in the substrate between the first logic cell and the second logic cell,
wherein the second device isolation layer extends along the common conductive line in the first direction.

7. The semiconductor device of claim 6 , wherein a plurality of contacts are included in the first logic cell and a plurality of contacts are included in the second logic cell, and further comprising:
a separating insulation layer separating the contacts of the first logic cell from the contacts of the second logic cell,
wherein the separating insulation extends in the first direction under the common conductive line, and
wherein the contacts of the first logic cell are aligned with the contacts of the second logic cell in the second direction.

8. The semiconductor device of claim 1 , wherein the gate structures extend from the PMOSFET region into the NMOSFET region.

9. A semiconductor device, comprising:
a substrate on which a plurality of logic cells are provided;
a plurality of active portions provided on the substrate and extending in a first direction;
contacts and gate structures extending in a second direction intersecting the first direction, the contacts and the gate structures alternately arranged;
a common conductive line extending along a boundary region of the plurality of logic cells in the first direction,
wherein at least one of the contacts is electrically connected to the common conductive line through a via therebetween,
wherein each of the contacts intersects a plurality of the active portions,
wherein end portions of the contacts are aligned with each other along the first direction,
wherein odd-numbered contacts of the contacts are electrically connected to the common conductive line through vias therebetween, and
wherein even-numbered contacts of the contacts are spaced apart from the common conductive line by an interlayer insulating layer therebetween.

10. The semiconductor device of claim 1 , wherein lengths of the contacts are substantially equal to each other.

11. A semiconductor device comprising:
a substrate on which a plurality of logic cells are provided, each logic cell including a P-type metal-oxide-semiconductor field effect transistor (PMOSFET) region and an N-type metal-oxide-semiconductor field effect transistor (NMOSFET) region;
a plurality of active portions provided on the substrate and extending in a first direction;
contacts and gate structures extending in a second direction intersecting the first direction, the contacts and the gate structures alternately arranged; and
a common conductive line extending along a boundary region of the plurality of logic cells in the first direction,
wherein at least one of the contacts is electrically connected to the common conductive line through a via therebetween,
wherein each of the contacts has a bar shape extending in the second direction and covers a plurality of the active portions, and
wherein end portions of the contacts are aligned with each other along the first direction.

12. The semiconductor device of claim 11 , wherein:
a first set of the contacts electrically connects to the common conductive line through a first set of vias; and
a second set of the contacts electrically connects to a conductive line different from the common conductive line through a second set of vias.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Sooyeon
• Sengupta Rwik
• Park Chulhong
• Chun Kwanyoung
• Lee Yusun
• Lee Hyun-Jong

Classifications

• H10D84/981

  Power supply lines · CPC title

• H10D84/961

  Substrate and well contacts · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/907 Primary

  CMOS gate arrays · CPC title

• H01L2027/11861

  Electricity · mapped topic