High aspect ratio buried power rail metallization
US-12148699-B2 · Nov 19, 2024 · US
US10224208B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10224208-B2 |
| Application number | US-201615150517-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 10, 2016 |
| Priority date | May 11, 2015 |
| Publication date | Mar 5, 2019 |
| Grant date | Mar 5, 2019 |
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An electroless plating process is performed on an Al layer, which is made of aluminum or an aluminum alloy, with an electroless plating liquid which is alkaline and contains a complexing agent. A plating method includes preparing a substrate 10 having a surface (for example, bottom surface of TSV 12) at which an Al layer 22 made of aluminum or an aluminum alloy is exposed; forming a zincate film 30 on a surface of the Al layer by performing a zincate treatment on the substrate; and forming a first electroless plating layer (for example, Co barrier layer 14a) on the surface of the Al layer with an electroless plating liquid (for example, Co-based plating liquid) which is alkaline and contains a complexing agent.
Opening claim text (preview).
We claim: 1. A plating method, comprising: preparing a substrate having a surface at which an Al layer made of aluminum or an aluminum alloy is exposed; forming a zincate film on a surface of the Al layer by performing a zincate treatment on the substrate; and forming a first electroless plating layer on the surface of the Al layer with an electroless plating liquid which is alkaline and contains a complexing agent, wherein the zincate film on the surface of the Al layer is substituted with the first electroless plating layer, the first electroless plating layer is a Co plating layer made of cobalt or a cobalt alloy, the surface of the substrate has a recess, the Al layer is an Al wiring layer having a surface exposed at a bottom surface of the recess, and in the forming of the first electroless plating layer, the first electroless plating layer is formed on the surface of the Al wiring layer which is exposed at the bottom surface of the recess, the method further comprises: forming a catalyst layer at least on a side surface of the recess after the forming of the first electroless plating layer; and forming, as a second electroless plating layer, a Co plating layer made of cobalt or a cobalt alloy on the bottom surface and the side surface of the recess, wherein the second electroless plating layer is a barrier layer. 2. The plating method of claim 1 , further comprising: burying a Cu plating layer made of copper or a copper alloy within the recess after the forming of the second electroless plating layer. 3. A computer-readable recording medium having stored thereon computer executable instructions that, in response to execution, cause a plating system to perform a plating method as claimed in claim 1 .
TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title
comprising etching via holes that stop on pads or on electrodes · CPC title
comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title
Barrier, adhesion or liner layers · CPC title
for electroless plating · CPC title
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