Semiconductor device

Patent metadata

Field	Value
Publication number	US-9780093-B2
Application number	US-201414162837-A
Country	US
Kind code	B2
Filing date	Jan 24, 2014
Priority date	Jul 2, 2010
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a substrate;
a first transistor over the substrate;
a second transistor over the substrate, and
a capacitor electrically connected to the first transistor and the second transistor,
wherein the first transistor and the second transistor are at least partially overlapped with each other with an insulating layer interposed there between,
wherein each of the first transistor and the second transistor comprises a channel formation region comprising an oxide semiconductor,
wherein a gate of the first transistor is directly connected to one of a source or a drain of the second transistor,
wherein the capacitor comprises a first electrode, a second electrode, and a first insulating layer provided between the first electrode and the second electrode, and
wherein the one of the source or the drain of the second transistor is the first electrode of the capacitor.

2. The semiconductor device according to claim 1 , wherein the oxide semiconductor comprises indium.

3. The semiconductor device according to claim 1 , wherein one of a source or a drain of the first transistor is connected to the other one of the source or the drain of the second transistor.

4. The semiconductor device according to claim 1 , wherein the oxide semiconductor contains hydrogen at a concentration lower than or equal to 5×10 19 atoms/cm 3 .

5. The semiconductor device according to claim 1 , wherein the oxide semiconductor contains carriers at a concentration lower than or equal to 1×10 12 /cm 3 .

6. The semiconductor device according to claim 1 , wherein off-state current per micrometer of a channel width of the second transistor is lower than or equal to 100 zA at room temperature.

7. The semiconductor device according to claim 1 , wherein a top surface of the gate of the first transistor is directly connected to a bottom surface of the one of the source or the drain of the second transistor.

8. A semiconductor device comprising:
a driver circuit comprising a first transistor, the first transistor comprising a channel formation region which comprises single crystal silicon;
a first insulating layer over the first transistor;
a second transistor over the first insulating layer;
a second insulating layer over the second transistor;
a third transistor over the second insulating layer, and
a capacitor electrically connected to the second transistor and the third transistor,
wherein each of the second transistor and the third transistor comprises a channel formation region comprising an oxide semiconductor,
wherein a gate of the second transistor is directly connected to one of a source or a drain of the third transistor,
wherein the second transistor and the third transistor are at least partially overlapped with each other,
wherein the capacitor comprises a first electrode, a second electrode, and a first insulating layer provided between the first electrode and the second electrode, and
wherein the one of the source or the drain of the third transistor is the first electrode of the capacitor.

9. The semiconductor device according to claim 8 , wherein the oxide semiconductor comprises indium.

10. The semiconductor device according to claim 8 , wherein one of a source or a drain of the second transistor is connected to the other one of the source or the drain of the third transistor.

11. The semiconductor device according to claim 8 , wherein the driver circuit comprises a selector circuit.

12. The semiconductor device according to claim 8 , wherein the channel formation region of the first transistor is formed in a single crystal silicon substrate.

13. The semiconductor device according to claim 8 , wherein the oxide semiconductor contains hydrogen at a concentration lower than or equal to 5×10 19 atoms/cm 3 .

14. The semiconductor device according to claim 8 , wherein the oxide semiconductor contains carriers at a concentration lower than or equal to 1×10 12 /cm 3 .

15. The semiconductor device according to claim 8 , wherein off-state current per micrometer of a channel width of the third transistor is lower than or equal to 100 zA at room temperature.

16. The semiconductor device according to claim 8 , wherein a top surface of the gate of the second transistor is directly connected to a bottom surface of the one of the source or the drain of the third transistor.

17. A semiconductor device comprising:
a substrate provided with a driver circuit, the substrate comprising single crystal silicon;
a first insulating layer over the substrate;
a first transistor over the first insulating layer;
a second insulating layer over the first transistor;
a second transistor over the second insulating layer; and
a capacitor electrically connected to the first transistor and the second transistor,
wherein each of the first transistor and the second transistor comprises a channel formation region comprising an oxide semiconductor,
wherein a gate of the first transistor is directly connected to one of a source or a drain of the second transistor, and
wherein the first transistor and the second transistor are at least partially overlapped with each other,
wherein the capacitor comprises a first electrode, a second electrode, and a first insulating layer provided between the first electrode and the second electrode, and
wherein the one of the source or the drain of the second transistor is the first electrode of the capacitor.

18. The semiconductor device according to claim 17 , wherein the oxide semiconductor comprises indium.

19. The semiconductor device according to claim 17 , wherein one of a source or a drain of the first transistor is connected to the other one of the source or the drain of the second transistor.

20. The semiconductor device according to claim 17 , wherein the driver circuit comprises a selector circuit.

21. The semiconductor device according to claim 17 , wherein the oxide semiconductor contains hydrogen at a concentration lower than or equal to 5×10 19 atoms/cm 3 .

22. The semiconductor device according to claim 17 , wherein the oxide semiconductor contains carriers at a concentration lower than or equal to 1×10 12 /cm 3 .

23. The semiconductor device according to claim 17 , wherein off-state current per micrometer of a channel width of the second transistor is lower than or equal to 100 zA at room temperature.

24. The semiconductor device according to claim 17 , wherein a top surface of the gate of the first transistor is directly connected to a bottom surface of the one of the source or the drain of the second transistor.

25. A semiconductor device comprising:
a substrate comprising single crystal silicon;
a first memory cell over the substrate, the first memory cell comprising a first transistor;
an insulating layer over the substrate; and
a second memory cell over the insulating layer, the second memory cell comprising a second transistor and a capacitor,
wherein each of the first transistor and the second transistor comprises a channel formation region comprising an oxide semiconductor,
wherein the first transistor and the second transistor are at least partially overlapped with each other,
wherein the capacitor comprises a first electrode, a second electrode, and a first insulating layer provided between the first electrode and the second electrode, and
wherein one of a source or a drain of the second transistor is the first el

Assignees

• Semiconductor Energy Lab

Inventors

• Kato Kiyoshi

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/0433

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• H01L27/1052 Primary

  Electricity · mapped topic