High bandwidth routing for die to die interposer and on-chip applications

Patent metadata

Field	Value
Publication number	US-10217708-B1
Application number	US-201715845978-A
Country	US
Kind code	B1
Filing date	Dec 18, 2017
Priority date	Dec 18, 2017
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

Routing structures including signal routing between die areas is described. In an embodiment, routing structures include signal lines with a characteristic thickness that is greater than a width. The signal lines may be twisted, and run directly underneath pads.

First claim

What is claimed is:

1. A routing structure comprising:
a first die area;
a second die area;
a signal routing connecting the first die area and the second die area, wherein the signal routing comprises:
a first group of stacked reference lines in a corresponding plurality of metal layers;
a second group of stacked reference lines in the corresponding plurality of metal layers;
a group of stacked trace lines horizontally between the first and second groups of stacked reference lines in the corresponding plurality of metal layers; and
a plurality of inter-layer switch regions and intra-layer switch regions interconnecting the group of stacked trace lines to form a bundle of twisted signal lines with corresponding signal paths that periodically change between the plurality of metal layers.

2. The routing structure of claim 1 , further comprising a plurality of pads directly over the group of stacked trace lines.

3. The routing structure of claim 2 , wherein each of the plurality of pads includes a vertex oriented orthogonal to a length of the bundle of twisted signal lines.

4. The routing structure of claim 1 , wherein each of the stacked trace lines is characterized by a corresponding thickness that is greater than a width.

5. The routing structure of claim 1 , wherein at least one of the plurality of intra-layer switch regions comprises a signal line switching to a vacated reference line area.

6. The routing structure of claim 5 , wherein a first plurality of the inter-layer switch regions comprise first vias characterized by approximately a same or smaller width than a minimum line width of the stacked reference lines the corresponding vias connect.

7. The routing structure of claim 1 , wherein a second plurality of the inter-layer switch regions comprise second vias characterized by approximately a same or smaller width than a minimum line width of the stacked trace lines the corresponding vias connect.

8. The routing structure of claim 1 , wherein the first group of stacked reference lines and the second group of stacked reference lines are electrically coupled, and share a same reference pad.

9. The routing structure of claim 1 , further comprising a capacitor adjacent the signal routing.

10. The routing structure of claim 1 , wherein the signal routing is formed in a substrate that is separate from the first and second die areas, and the first and second die areas are discrete chips.

11. The routing structure of claim 1 , wherein the signal routing is formed on a silicon layer that includes both the first and second die areas, such that the signal routing, first die area, and second die area are part of a single chip.

Assignees

• Apple Inc

Inventors

• Dabral Sanjay
• Secker David A
• Chen Huabo
• Cheng Zhenggang

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/07252

  changes in structures or sizes · CPC title

• H10W72/01225

  in solid form, e.g. by using a powder or by stud bumping · CPC title