Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2016267971-A1
Application number	US-201615055284-A
Country	US
Kind code	A1
Filing date	Feb 26, 2016
Priority date	Mar 10, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

A semiconductor memory device includes a first memory cell array electrically connected to a set of first bit lines, a second memory cell array electrically connected to a set of second bit lines, and a sense amplifier module that is physically located between the first and second memory cell arrays, and shared by the first and second memory cell arrays.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a first memory cell array electrically connected to a set of first bit lines; a second memory cell array electrically connected to a set of second bit lines; and a sense amplifier module that is physically located between the first and second memory cell arrays, and shared by the first and second memory cell arrays.

2 . The semiconductor memory device according to claim 1 , wherein
the sense amplifier module includes sense amplifier units, each of which is connected to a corresponding one of the first bit lines and a corresponding one of the second bit lines.

3 . The semiconductor memory device according to claim 2 , further comprising:
a first switching circuit connected between the sense amplifier units and the first bit lines, the first switching circuit being controlled to electrically connect and disconnect the sense amplifier units and the first bit lines, and a second switching circuit connected between the sense amplifier units and the second bit lines, the second switching circuit being controlled to electrically connect and disconnect the sense amplifier units and the second bit lines.

4 . The semiconductor memory device according to claim 3 ,
wherein each of the first and second switching circuits includes high voltage-resistant transistors.

5 . The semiconductor memory device according to claim 3 ,
wherein each of the first and second switching circuits includes low voltage-resistant transistors.

6 . The semiconductor memory device according to claim 3 , wherein
the first and second memory cell arrays, the sense amplifier module, and the first and second switching circuits are formed on the same well area.

7 . The semiconductor memory device according to claim 1 , further comprising:
a data cache configured to cache data transmitted from the sense amplifier module to an input/output circuit and to cache data transmitted from the input/output circuit to the sense amplifier module, wherein the data cache is physically located adjacent to the second memory cell array such that the sense amplifier module and the second memory cell array are between the first memory cell array and the data cache.

8 . The semiconductor memory device according to claim 7 , wherein the sense amplifier module includes a first latch circuit and the data cache includes a second latch circuit electrically connected to the first latch circuit.

9 . The semiconductor memory device according to claim 8 , wherein the first latch circuit includes a first latch that is electrically connected to a first set of the sense amplifier units through a first bus and a second latch that is electrically connected to a second set of the sense amplifier units through a second bus.

10 . The semiconductor memory device according to claim 9 , wherein the sense amplifier module further includes a first pre-charge circuit and a first discharge circuit for the first bus, and a second pre-charge circuit and a second discharge circuit for the second bus.

11 . The semiconductor memory device according to claim 7 , further comprising:
a switching circuit that is controlled to electrically connect and disconnect the sense amplifier units and the data cache, wherein the switching circuit includes high voltage-resistant transistors and is physically located between the second memory cell array and the data cache.

12 . The semiconductor memory device according to claim 7 , further comprising:
a switching circuit that is controlled to electrically connect and disconnect the sense amplifier units and a power supply, wherein the switching circuit includes high voltage-resistant transistors and is physically located between the second memory cell array and the data cache.

13 . The semiconductor memory device according to claim 12 , further comprising:
a first wiring that connects the sense amplifier units and the data cache, the first wiring passing over an area of the second memory cell array.

14 . The semiconductor memory device according to claim 13 , further comprising:
a second wiring that connects the sense amplifier units and the power supply, and the second wiring passing over an area of the second memory cell array.

15 . A semiconductor memory device comprising:
first and second memory cell arrays formed on a substrate; and sense amplifier units for the first and second memory cell arrays formed on the substrate between the first and second memory cell arrays.

16 . The semiconductor memory device according to claim 15 , further comprising:
a first switching circuit that is controlled to electrically connect and disconnect the first memory cell array and the sense amplifier units, and formed on the substrate between the first memory cell array and the sense amplifier units, and a second switching circuit that is controlled to electrically connect and disconnect the second memory cell array and the sense amplifier units, and formed on the substrate between the second memory cell array and the sense amplifier units.

17 . The semiconductor memory device according to claim 16 , further comprising:
a data cache configured to cache data transmitted from the sense amplifier units to an input/output circuit and to cache data transmitted from the input/output circuit to the sense amplifier units, wherein the data cache is formed on the substrate adjacent to the second memory cell array such that the first and second switching circuits, the sense amplifier units, and the second memory cell array are between the first memory cell array and the data cache.

18 . The semiconductor memory device according to claim 17 , further comprising:
a first latch that is electrically connected to a first set of the sense amplifier units through a first bus and a second latch that is electrically connected to a second set of the sense amplifier units through a second bus.

19 . The semiconductor memory device according to claim 18 , wherein the data cache includes a third latch that is electrically connected to both the first and second latches through a third bus.

20 . The semiconductor memory device according to claim 19 , further comprising a first pre-charge circuit and a first discharge circuit for the first bus, and a second pre-charge circuit and a second discharge circuit for the second bus.

Assignees

• Toshiba Kk

Inventors

• Maejima Hiroshi

Classifications

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/02

  electrically programmable · CPC title

• G11C7/1048

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title