Folded channel trench MOSFET

US10199492B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10199492-B2
Application numberUS-201615364827-A
CountryUS
Kind codeB2
Filing dateNov 30, 2016
Priority dateNov 30, 2016
Publication dateFeb 5, 2019
Grant dateFeb 5, 2019

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A trench MOSFET device includes a body, region and source region that undulate along a channel width direction of the MOSFET device such that the body region and source region have variations in depth along the channel width direction. The undulations increase a channel width of the MOSFET device.

First claim

Opening claim text (preview).

What is claimed is: 1. A trench MOSFET device, comprising: a lightly doped epitaxial layer of a first conductivity type provided on a heavily doped semiconductor substrate of the first conductivity type; a gate trench filled with a conductive material extending into the lightly doped epitaxial layer; a body region of a second conductivity type opposite to the first conductivity type provided in portions of the lightly doped epitaxial layer, wherein the body region have a first undulation along a channel width direction; and a source region of the first conductivity type provided in top portions of the body region, wherein the source region have a second undulation along the channel width direction above the first undulation, wherein a channel width of the MOSFET device is increased with introduction of the first and second undulations wherein the lightly doped epitaxial layer has a third undulation along a channel width direction of the MOSFET device with a depth extending into the semiconductor substrate deeper than other portions of the lightly doped epitaxial layer. 2. The device of claim 1 , wherein the first conductivity type is an N type and the second conductivity type is a P type. 3. The device of claim 1 , wherein the lightly doped epitaxial layer, the body region and the source region have variations in depth along the channel width. 4. The device of claim 1 , wherein the first undulation has a depth extending into the lightly doped epitaxial layer deeper than other portions of the body region. 5. The device of claim 1 , wherein the second undulation has a depth extending into the body region deeper than other portions of the source region. 6. The device of claim 1 , wherein tapered sides of the first and second undulations are at an angle between about 25 degrees and about 90 degrees.

Assignees

Inventors

Classifications

  • using masks · CPC title

  • Cross-sectional shapes or dispositions of interconnections · CPC title

  • by forming self-aligned vias or self-aligned contact plugs · CPC title

  • by filling conductive material into holes, grooves or trenches · CPC title

  • Electricity · mapped topic

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10199492B2 cover?
A trench MOSFET device includes a body, region and source region that undulate along a channel width direction of the MOSFET device such that the body region and source region have variations in depth along the channel width direction. The undulations increase a channel width of the MOSFET device.
Who is the assignee on this patent?
Alpha & Omega Semiconductor
What technology area does this patent fall under?
Primary CPC classification H01L29/7813. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 05 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).