Nonvolatile memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10199390-B2
Application number	US-201715644290-A
Country	US
Kind code	B2
Filing date	Jul 7, 2017
Priority date	Feb 16, 2009
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

First claim

What is claimed is:

1. A nonvolatile memory device, comprising:
a semiconductor pattern extending from the semiconductor substrate;
a stack structure including a plurality of gate electrodes and a plurality of insulating patterns alternately and vertically stacked on the semiconductor substrate;
a trench spaced apart from the semiconductor pattern and penetrating the stacked structure; and
a charge storage layer disposed between the gate electrodes and the semiconductor pattern, the charge storage layer including a charge blocking layer comprising Al 2 O 3 ,
wherein each of the gate electrodes has a first sidewall adjacent to the semiconductor pattern, and each of the insulating patterns has a second sidewall adjacent to the trench,
wherein the charge storage layer covering the first sidewalls of the gate electrodes and the second sidewalls of the insulating patterns, and
wherein each of the gate electrodes includes a metal pattern and a metal liner pattern between a sidewall of the metal pattern and the charge storage layer.

2. The nonvolatile memory device of claim 1 , wherein the metal liner pattern is in contact with a top surface and a bottom surface of the metal pattern.

3. The nonvolatile memory device of claim 1 , further comprising a separation insulating layer filling the trench.

4. The nonvolatile memory device of claim 3 , wherein the separation insulating layer covers portions of the charge storage layer disposed on the second sidewalls of the insulating patterns.

5. The nonvolatile memory device of claim 3 , wherein the gate electrodes are in contact with the separation insulating layer.

6. A nonvolatile memory device, comprising:
stacked structures including a plurality of gate electrodes and a plurality of insulating patterns alternately and vertically stacked on a semiconductor substrate and extending in a first direction;
first and second semiconductor patterns disposed between the adjacent ones of the stacked structures and spaced apart from each other, the first and second semiconductor patterns crossing sidewalls of the stacked structures; and
a charge blocking layer disposed between the first semiconductor pattern and the plurality of gates electrodes and between the second semiconductor pattern and the plurality of gate electrodes.

7. The nonvolatile memory device of claim 6 , further comprising a buried insulating layer between the first and second semiconductor patterns.

8. The nonvolatile memory device of claim 6 , wherein a metal liner pattern is formed between the charge blocking layer and the plurality of gate electrodes and is formed on a top surface and a bottom surface of each of the plurality of gate electrodes.

9. The nonvolatile memory device of claim 6 , Wherein a charge storage layer disposed between the first semiconductor pattern and the plurality of gate electrodes and between the second semiconductor pattern and the plurality of gate electrodes.

10. The nonvolatile memory device of claim 6 , Wherein each of the first and second semiconductor patterns has a line shape extending in a vertical direction perpendicular to a top surface of the semiconductor substrate.

11. A nonvolatile memory device comprising:
stacked structures including a plurality of gate electrodes and a plurality of insulating patterns alternately and vertically stacked on a semiconductor substrate and extending in a first direction; and
first and second semiconductor patterns disposed between the adjacent ones of the stacked structures and spaced apart from each other,the first and second semiconductor patterns crossing sidewalls of the stacked structures;
wherein each of the plurality of gate electrodes includes a metal pattern and a metal liner pattern between the metal pattern and the first semiconductor patterns, and
wherein the metal liner pattern is formed on a top surface and a bottom surface of each of the plurality of gate electrodes.

12. The nonvolatile memory device of claim 11 , further comprising a separation insulating layer spaced apart from the first and second semiconductor patterns and extending in the first direction on the semiconductor substrate.

13. The nonvolatile memory device of claim 11 , further comprising a charge storage layer disposed between the first semiconductor pattern and the plurality of gate electrodes and between the second semiconductor pattern and the plurality of gate electrodes; and
a separation insulating layer spaced apart from the first and second semiconductor patterns and extending in the first direction on the semiconductor substrate,
wherein portions of the charge storage layer are between the separation insulating layer and sidewalls of the insulating patterns.

14. The nonvolatile memory device of claim 11 , wherein each of the first and second semiconductor patterns has a line shape extending in a vertical direction perpendicular to a top surface of the semiconductor substrate.

15. The nonvolatile memory device of claim 12 , wherein the separation insulating layers covers sidewalls of the gate electrodes.

16. The nonvolatile memory device of claim 14 , further comprising a charge blocking layer formed between each of the first and second semiconductor patterns and the plurality of gate electrodes and formed on a top surface and a bottom surface of each of the plurality of gate electrodes.

17. The nonvolatile memory device of claim 14 , further comprising a charge storage layer disposed between the first semiconductor pattern and the plurality of gate electrodes and between the second semiconductor pattern and the plurality of gate electrodes.

18. The nonvolatile memory device of claim 14 , further comprising a separation insulating layer spaced apart from the first and second semiconductor patterns and extending in the first direction on the semiconductor substrate.

19. The nonvolatile memory device of claim 16 , wherein the metal liner pattern is formed between the charge blocking layer and the plurality of gate electrodes and is formed on a top surface and a bottom surface of each of the plurality of gate electrodes.

20. The nonvolatile memory device of claim 18 , wherein the separation insulating layers covers sidewalls of the plurality of gate electrodes.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Sunwoo
• Lee Sangwoo
• Lee Changwon
• Lee Jeonggil

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L29/4958

  Electricity · mapped topic

• H01L23/535

  Electricity · mapped topic

• H01L27/1159

  Electricity · mapped topic

• H01L29/4966

  Electricity · mapped topic