Nonvolatile memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9343478-B2
Application number	US-201414486547-A
Country	US
Kind code	B2
Filing date	Sep 15, 2014
Priority date	Feb 16, 2009
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a stack structure including a plurality of gate electrodes and a plurality of insulating patterns alternately and vertically stacked on a substrate;
a channel structure penetrating the stack structure; and
a charge storage layer formed between the channel structure and the stack structure,
wherein each of the gate electrodes includes a metal pattern and a metal liner pattern between the metal pattern and the channel structure.

2. The nonvolatile memory device of claim 1 , wherein the metal liner pattern covers a top surface and a bottom surface of the metal pattern.

3. The nonvolatile memory device of claim 1 , wherein each of the gate electrodes has upper and lower surfaces completely covered by the insulating patterns.

4. The nonvolatile memory device of claim 1 , further comprising an insulating layer penetrating the stack structure and spaced apart from the channel structure,
wherein the insulating layer is in contact with the metal pattern and the metal liner pattern.

5. The nonvolatile memory device of claim 4 , wherein the gate electrodes do not laterally extend beyond a boundary between the insulating layer and the insulating patterns.

6. The nonvolatile memory device of claim 1 , wherein the metal pattern comprises one of Co, Ni, W, Mo and Ti.

7. The nonvolatile memory device of claim 1 , wherein the metal liner pattern comprises one of TiN, TaN and WN.

8. A nonvolatile memory device comprising:
a stack structure including a plurality of gate electrodes and a plurality of insulating patterns alternately and vertically stacked on a substrate;
a channel structure penetrating the stack structure;
an insulating layer penetrating the stack structure and spaced apart from the channel structure, and
a charge storage layer formed between the channel structure and the stack structure,
wherein each of the gate electrodes includes a metal pattern and a metal liner pattern between the metal pattern and the channel structure, and
wherein the insulating layer has a sidewall covering sidewalls of the gate electrodes and the insulating patterns, and the sidewall of the insulating layer is in contact with the metal patterns and the metal liner patterns of the gate electrodes.

9. The nonvolatile memory device of claim 8 , wherein the gate electrodes are not laterally extend beyond a boundary between the insulating layer and the insulating patterns.

10. The nonvolatile memory device of claim 8 , wherein each of the gate electrodes has upper and lower surfaces completely covered by the insulating patterns.

11. The nonvolatile memory device of claim 8 , wherein the metal liner pattern covers a top surface and a bottom surface of the metal pattern.

12. The nonvolatile memory device of claim 8 , wherein the metal pattern comprises one of Co, Ni, W, Mo and Ti.

13. The nonvolatile memory device of claim 8 , wherein the metal liner pattern comprises one of TiN, TaN and WN.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Sunwoo
• Lee Sangwoo
• Lee Changwon
• Lee Jeonggil

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D64/666

  the conductor further comprising additional layers · CPC title

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title