Non-volatile memory device

Patent metadata

Field	Value
Publication number	US-10199389-B2
Application number	US-201715485334-A
Country	US
Kind code	B2
Filing date	Apr 12, 2017
Priority date	Sep 25, 2015
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

First claim

What is claimed is:

1. A non-volatile memory device comprising:
a channel structure that is located on a substrate and extends perpendicularly to the substrate;
a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure;
an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated; and
an insulating layer that is in contact with a top surface of the conductive pattern and is formed along side surfaces of the electrode structure,
wherein the top surface of the conductive pattern is formed to be lower than a top surface of the channel structure.

2. The non-volatile memory device of claim 1 , wherein the top surface of the conductive pattern is formed to be higher than a top surface of the substrate.

3. The non-volatile memory device of claim 1 , further comprising:
a spacer that is disposed between the conductive pattern and the electrode structure and is formed along side surfaces of the conductive pattern and side surfaces of the insulating layer, and
a bottom surface of the conductive pattern is formed to be lower than a bottom surface of the spacer.

4. The non-volatile memory device of claim 1 , further comprising:
a first interlayer insulating film that covers the channel structure and the electrode structure; and
a metal contact structure that is in contact with the top surface of the conductive pattern through the first interlayer insulating film.

5. The non-volatile memory device of claim 4 , further comprising:
a second interlayer insulating film that covers the first insulating interlayer film;
a first conductive stud that is disposed on the metal contact structure through the second interlayer insulating film; and
a second conductive stud that is disposed on the channel structure through the first and second interlayer insulating films.

6. The non-volatile memory device of claim 5 , wherein the first conductive stud and a metal contact of the metal contact structure are integrally formed.

7. A non-volatile memory device comprising:
a plurality of channel structures that is located on a substrate and extends perpendicularly to the substrate;
a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure;
a first interlayer insulating film that covers a plurality of channel structures and the conductive pattern; and
a metal contact that is disposed on the conductive pattern, is electrically connected to the conductive pattern, passes through the first interlayer insulating film, and has a bottom surface formed to be lower than top surfaces of the plurality of channel structures.

8. The non-volatile memory device of claim 7 , wherein a top surface of the conductive pattern is formed to be higher than a top surface of the substrate and to be lower than the top surfaces of the plurality of channel structures.

9. The non-volatile memory device of claim 7 , wherein the plurality of channel structures are disposed in a honeycomb pattern.

10. The non-volatile memory device of claim 7 , wherein the conductive pattern comprises a first portion including the metal contact, and a second portion adjacent to the first portion, and
a width of the first portion measured in a first direction parallel to a top surface of the substrate is larger than a width of the second portion measured in the first direction.

11. A non-volatile memory device comprising:
first and second channel structures that are located on a substrate and extend perpendicularly to the substrate;
a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the first and second channel structures;
a first interlayer insulating film that covers the first and second channel structures and the conductive pattern;
a second interlayer insulating film that covers the first interlayer insulating film;
a metal contact that is disposed on the conductive pattern and penetrates through the first interlayer insulating film;
a first conductive stud that is disposed on the metal contact, penetrates through the second interlayer insulating film and is electrically connected to the conductive pattern; and
a second conductive stud that is disposed only on the first channel structure, is not disposed on the second channel structure and penetrates through the first and second interlayer insulating films.

12. The non-volatile memory device of claim 11 , wherein a distance between the first channel structure and the metal contact is larger than a distance between the first channel structure and the metal contact.

13. The non-volatile memory device of claim 11 , wherein a top surface of the conductive pattern is formed to be lower than top surfaces of the channel structures.

14. A non-volatile memory device comprising:
a vertical NAND string that is located on a substrate and extends perpendicularly to the substrate, the vertical NAND string comprising a plurality of serially connected memory cells; and
a common source line that is spaced apart from the vertical NAND string, and that extends perpendicularly from a first location in contact with the substrate to a second location at least as high as the top of the vertical NAND string, the common source line comprising a conductive pattern extending from the first location to a height at least as high as a first memory cell of the plurality of serially connected memory cells and a metal contact electrically connected to the conductive pattern and extending from the second location to a depth of a portion of the vertical NAND string.

15. The non-volatile memory device of claim 14 , further comprising an electrode structure that is located between the vertical NAND string and the common source line, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated above the substrate,
wherein the height of the first location above the substrate is at a height below the third closest gate pattern to the substrate of said electrode structure.

16. The non-volatile memory device of claim 15 , further comprising an insulating layer that contacts a top surface of the common source line and is formed along side surfaces of the electrode structure.

17. The non-volatile memory device of claim 15 , further comprising:
a first interlayer insulating film that covers the vertical NAND string and the electrode structure,
wherein the metal contact extends through the first interlayer insulating film and contacts a top surface of the conductive pattern.

18. The non-volatile memory device of claim 17 , wherein the common source line is formed within a contact hole extending at least between the second location to the first location.

19. A non-volatile memory device comprising:
a channel disposed on a substrate and extending in a first direction that is substantially perpendicular to the substrate;
a first conductive pattern contacting the substrate and extending in the first direction, the first conductive pattern spaced apart from the channel, wherein the first conductive pattern is a line type extending in a second direction that is substantially perpendicular with respect to the first direction;
a second conductive pattern disposed on the first conductive pattern;
a plurality of electrodes stacked in the first direction comprising a first electrode and a second electrode, the first electrode dispo

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jong-Won
• Kang Chang-Seok
• Park Young-Woo
• Lee Jae-Goo
• Lee Jae-Duk

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H01L27/1157

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L23/5283

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic