Non-volatile memory device

Patent metadata

Field	Value
Publication number	US-9646984-B2
Application number	US-201615264902-A
Country	US
Kind code	B2
Filing date	Sep 14, 2016
Priority date	Sep 25, 2015
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

First claim

What is claimed is:

1. A non-volatile memory device comprising:
a channel disposed on a substrate and extending in a first direction that is substantially perpendicular to the substrate;
a first conductive pattern contacting the substrate and extending in the first direction, the first conductive pattern spaced apart from the channel, wherein the first conductive pattern is a line type extending in a second direction that is substantially perpendicular with respect to the first direction;
a second conductive pattern disposed on the first conductive pattern, the second conductive pattern extending in the first direction;
a plurality of electrodes stacked in the first direction comprising a first electrode and a second electrode, the first electrode disposed between the channel and the first conductive pattern, the second electrode disposed between the channel and the second conductive pattern;
a first barrier layer extending in the first direction along a side of the first conductive pattern and a side of the second conductive pattern; and
a second barrier layer extending in the first direction along the side of the second conductive pattern,
wherein the second electrode is the top most electrode among the plurality of electrodes and a bottom surface of the second conductive pattern is disposed lower than a bottom surface of the second electrode.

2. The non-volatile memory device of claim 1 , wherein the first conductive pattern comprises polysilicon.

3. The non-volatile memory device of claim 1 , wherein a top surface of the first conductive pattern is disposed above a top surface of the substrate.

4. The non-volatile memory device of claim 1 , further comprising a first interlayer insulating film that covers the channel and the plurality of electrodes.

5. The non-volatile memory device of claim 4 , further comprising a second interlayer insulating film that covers the first interlayer insulating film.

6. The non-volatile memory device of claim 5 , further comprising:
a first conductive stud that is disposed on the second conductive pattern through the second interlayer insulating film; and
a second conductive stud that is disposed on the channel through the first and second interlayer insulating films.

7. The non-volatile memory device of claim 1 , wherein the first barrier layer comprises silicon oxide and the second barrier layer comprises at least one of HfO2, Al2O3, ZrO2 and TaO2.

8. A non-volatile memory device comprising:
a vertical NAND string that is disposed on a substrate and extends substantially perpendicularly to the substrate, the vertical NAND string comprising a plurality of serially connected memory cells, a String Selection Line (SSL) and a Ground Selection Line (GSL); and
a common source line that is spaced apart from the vertical NAND string, and that extends substantially perpendicularly from a first end in contact with the substrate to a second end disposed under a bottom surface of the SSL, wherein the common source line comprises polysilicon.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jong-Won
• Kang Chang-Seok
• Park Young-Woo
• Lee Jae-Goo
• Lee Jae-Duk

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H01L27/11582

  Electricity · mapped topic

• H01L27/1157 Primary

  Electricity · mapped topic

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title