Semiconductor memory

Patent metadata

Field	Value
Publication number	US-9502299-B2
Application number	US-201414475440-A
Country	US
Kind code	B2
Filing date	Sep 2, 2014
Priority date	Mar 13, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

First claim

What is claimed is:

1. A semiconductor memory comprising:
a first memory cell region that includes multiple first memory cells stacked above a semiconductor substrate;
a second memory cell region that includes multiple second memory cells stacked above the semiconductor substrate;
first and second dummy regions on opposite sides of the first memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, the first dummy region being provided between the first memory cell region and the second memory cell region;
a first wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate; and
a plurality of second wiring provided above the first memory cell region and electrically connected to the multiple first memory cells; wherein
the plurality of second wiring overlap the first and second dummy regions in a first direction crossing a surface of the semiconductor substrate.

2. The memory according to claim 1 , wherein
the first memory cell region includes multiple conductive layers that are stacked above the semiconductor substrate and multiple semiconductor pillars extending through the conductive layers, the first memory cells being located at intersections of the conductive layers and the semiconductor pillars.

3. The memory according to claim 2 , wherein
each of the multiple conductive layers has a planar shape and includes first and second conductive layers at a same level above the semiconductor substrate, each having a plurality of protruding portions that are interleaved with a plurality of protruding portions of the other.

4. The memory according to claim 3 , wherein a first group of the semiconductor pillars extends through the protruding portions of the first conductive layers at different levels and a second group of the semiconductor pillars extends through the protruding portions of the second conductive layers at different levels.

5. The memory according to claim 4 , wherein
the conductive layers at each level is surrounded by a wiring that electrically connects dummy cells of the first and second dummy regions that are at the same level.

6. The memory according to claim 1 , wherein
the first memory cell region and the dummy regions include multiple conductive layers that are stacked above the semiconductor substrate and multiple semiconductor pillars extending through the conductive layers, the first memory cells being located at intersections of the conductive layers and the semiconductor pillars in the first memory cell region and the dummy cells being located at intersections of the conductive layers and the semiconductor pillars in the dummy regions.

7. The memory according to claim 6 , wherein
each of the multiple conductive layers has a planar shape and includes first, second, third, and fourth conductive layers that are at a same level above the semiconductor substrate, and
the first and second conductive layers are in the first memory cell region, and the third and fourth conductive layers are in the first and second dummy regions, respectively, and electrically connected to each other.

8. The memory according to claim 7 , wherein the first and second conductive layers of the same level above the semiconductor substrate each have a plurality of protruding portions that are interleaved with the plurality of protruding portions of the other.

9. The memory according to claim 7 , wherein the third and fourth conductive layers surround the first and second conductive layers that are at the same level above the semiconductor substrate as the third and fourth conductive layers.

10. The memory according to claim 1 , wherein
the plurality of second wiring are electrically connected to the dummy cells.

11. The memory according to claim 1 , wherein
the plurality of second wiring are electrically connected to the multiple second memory cells.

12. The memory according to claim 1 , wherein
the first memory cell region includes multiple conductive layers that are stacked above the semiconductor substrate, each of the multiple conductive layers having a planar shape and including first and second conductive layers at a same level above the semiconductor substrate, the first conductive layer having a protruding portion that protrudes towards the second conductive layer.

13. A semiconductor memory comprising:
a plurality of memory blocks including first, second, and third memory blocks;
a first dummy region between the first memory block and the second memory block, the first dummy region including a first dummy cell;
a second dummy region between the second memory block and the third memory block, the second dummy region including a second dummy cell having a gate that is electrically connected to a gate of the first dummy cell; and
a plurality of bit lines provided above the first, second, and third memory blocks and electrically connected to memory cells of the first, second, and third memory blocks, wherein
the plurality of bit lines extend above the first and second dummy regions.

14. The memory according to claim 13 , wherein
each of the memory blocks includes multiple conductive layers that are stacked above the semiconductor substrate and multiple semiconductor pillars extending through the conductive layers, memory cells of the memory blocks being located at intersections of the conductive layers and the semiconductor pillars.

15. The memory according to claim 14 , wherein
each of the multiple conductive layers has a planar shape and, for each memory block, includes first and second conductive layers at a same level above the semiconductor substrate, each having a plurality of protruding portions that are interleaved with a plurality of protruding portions of the other.

16. The memory according to claim 15 , wherein
for each memory block, the first conductive layer surrounds the second conductive layer at the same level above the semiconductor substrate as the first conductive layer.

17. The memory according to claim 16 , wherein
for each memory block, the first conductive layer at each level is surrounded by a wiring that electrically connects dummy cells of the first and second dummy regions that are at the same level.

18. The memory according to claim 17 , wherein a first group of the semiconductor pillars extends through the protruding portions of the first conductive layers at different levels and a second group of the semiconductor pillars extends through the protruding portions of the second conductive layers at different levels.

19. The memory according to claim 13 , wherein
the plurality of bit lines are electrically connected to the dummy cells.

20. The memory according to claim 13 , wherein
each of the memory blocks includes multiple conductive layers that are stacked above the semiconductor substrate, each of the multiple conductive layers having a planar shape and including first and second conductive layers at a same level above the semiconductor substrate, the first conductive layer having a protruding portion that protrudes towards the second conductive layer.

Assignees

• Toshiba Kk

Inventors

• Hishida Tomoo
• Murakami Sadatoshi
• Katsumata Ryota
• Iwase Masao

Classifications

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H01L27/1157

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L21/823437 Primary

  Electricity · mapped topic