Semiconductor memory

Patent metadata

Field	Value
Publication number	US-9768188-B2
Application number	US-201615349907-A
Country	US
Kind code	B2
Filing date	Nov 11, 2016
Priority date	Mar 13, 2014
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

First claim

What is claimed is:

1. A memory comprising:
a plurality of memory cells including a first memory cell above a semiconductor substrate and a second memory cell above the first memory cell;
a first interconnection including a first part and a second part and surrounding the plurality of memory cells such that the plurality of memory cells are between the first part and the second part; and
a second interconnection above the plurality of memory cells, the first part, and the second part, and electrically connected to at least one of the first memory cell and the second memory cell.

2. The memory according to claim 1 , wherein the second interconnection extends in a first direction.

3. The memory according to claim 2 , wherein a height of the first interconnection with respect to the semiconductor substrate is the same as that of the first memory cell.

4. The memory according to claim 3 , further comprising:
a third interconnection above the first interconnection and surrounding the plurality of memory cells.

5. The memory according to claim 2 , wherein a height of the first interconnection with respect to the semiconductor substrate is the same as that of the second memory cell.

6. The memory according to claim 1 , further comprising:
a third interconnection above the first interconnection and surrounding the plurality of memory cells.

7. A memory comprising:
a semiconductor substrate;
a plurality of pillars extending in a first direction orthogonal to the semiconductor substrate;
a plurality of word lines stacked above the semiconductor substrate, one of the word lines surrounding a part of one of the pillars;
a plurality of first interconnections stacked above the semiconductor substrate, the first interconnections including a first part and a second part and surrounding the plurality of word lines and the plurality of pillars such that the pillars are between the first part and the second part; and
a plurality of second interconnections above the plurality of memory cells, the first part, and the second part, and electrically connected to the plurality of pillars.

8. The memory according to claim 7 , wherein the second interconnections extend in a second direction orthogonal to the first direction.

9. A memory comprising:
a memory cell region including a plurality of memory cells including a first memory cell above a semiconductor substrate and a second memory cell above the first memory cell;
a dummy cell region including a first interconnection, wherein the first interconnection includes first and second parts that are electrically connected to each other and surrounds the plurality of memory cells such that the plurality of memory cells are between the first part and the second part; and
a second interconnection directly above the plurality of memory cells, the first part, and the second part in a stacking direction of the memory cells, and electrically connected to at least one of the first memory cell and the second memory cell.

10. The memory according to claim 9 , wherein
the dummy cell region includes a first dummy region on a first side of the memory cell region, and a second dummy region on a second side of the memory cell region, and
the first and second sides of the memory cell region are opposite sides of the memory cell region in a direction along which the second interconnection extends.

11. The memory according to claim 10 , wherein
the first dummy region includes first dummy cells and the first part of the first interconnection, and
the second dummy region includes second dummy cells and the second part of the first interconnection.

12. The memory according to claim 11 , wherein during testing of the memory, a test voltage is applied to the first interconnection to detect whether or not a short circuit exists between the memory cell region and the first dummy region and between the memory cell region and the second dummy region.

13. The memory according to claim 9 , wherein the second interconnection extends in a first direction that cross the stacking direction.

14. The memory according to claim 13 , wherein a height of the first interconnection in the stacking direction with respect to the semiconductor substrate is the same as that of the first memory cell.

15. The memory according to claim 14 , wherein the dummy cell region further includes a third interconnection above the first interconnection and surrounding the plurality of memory cells.

16. The memory according to claim 12 , wherein a height of the first interconnection in the stacking direction with respect to the semiconductor substrate is the same as that of the second memory cell.

17. The memory according to claim 9 , wherein the dummy cell region further includes a third interconnection above the first interconnection and surrounding the plurality of memory cells.

Assignees

• Toshiba Memory Corp

Inventors

• Hishida Tomoo
• Murakami Sadatoshi
• Katsumata Ryota
• Iwase Masao

Classifications

• H01L27/1157 Primary

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic

• H01L21/823437

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H10D84/0135

  Manufacturing their gate conductors · CPC title