Semiconductor wafer and method

Patent metadata

Field	Value
Publication number	US-10199216-B2
Application number	US-201514757896-A
Country	US
Kind code	B2
Filing date	Dec 24, 2015
Priority date	Dec 24, 2015
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

In an embodiment, a method includes treating an edge region of a wafer including a substrate having an upper surface and one or more epitaxial Group III nitride layers arranged on the upper surface of the substrate, so as to remove material including at least one Group III element from the edge region.

First claim

What is claimed is:

1. A method of processing a wafer including a substrate having an upper surface, a rear surface opposite the upper surface and a side face between the rear surface and the upper surface, the method comprising:
forming Group III nitride material on the upper surface and the side face of the substrate;
removing the Group III nitride material from the side face of the substrate and from a peripheral region of the upper surface of the substrate, the peripheral region bounding an active area of the upper surface, wherein the Group III nitride material that remains on the active area comprises one or more epitaxial Group III nitride layers; and
after removing the Group III nitride material from the side face of the substrate and from the peripheral region of the upper surface of the substrate, depositing a covering layer onto the peripheral region of the upper surface of the substrate, the side face of the substrate and the rear surface of the substrate.

2. The method of claim 1 , wherein the Group III nitride material removed from the peripheral region of the upper surface of the substrate has poorer epitaxy compared to the Group III nitride material that remains on the active area of the upper surface.

3. The method of claim 1 , wherein the peripheral region comprises an upper bevel extending between the upper surface of the substrate and the side face of the substrate, and wherein the Group III nitride material is removed from the upper bevel.

4. The method of claim 1 , wherein the Group III nitride material removed from the peripheral region of the upper surface of the substrate comprises a polycrystalline group III nitride layer.

5. The method of claim 1 , wherein removing the Group III nitride material from the side face of the substrate and from the peripheral region of the upper surface of the substrate comprises mechanically removing the Group III nitride material from the side face and from the peripheral region.

6. The method of claim 5 , wherein mechanically removing the Group III nitride material from the side face of the substrate and from the peripheral region of the upper surface of the substrate comprises at least one of edge cutting, grinding, lapping, polishing and dry etching.

7. The method of claim 1 , wherein removing the Group III nitride material from the side face of the substrate and from the peripheral region of the upper surface of the substrate comprises wet etching the Group III nitride material from the side face and from the peripheral region.

8. The method of claim 7 , further comprising applying a mask to the one or more epitaxial Group III nitride layers on the active area of the upper surface of the substrate before removing the Group III nitride material from the side face of the substrate and from the peripheral region of the upper surface of the substrate.

9. The method of claim 1 , wherein removing the Group III nitride material from the side face of the substrate and from the peripheral region of the upper surface of the substrate comprises removing an upper portion of a layer comprising a Group III-nitride from at least an upper bevel of the substrate by dry etching, followed by removing an underlying portion of the layer comprising a Group III-nitride by wet etching.

10. A method of processing a wafer including a substrate having an upper surface, a rear surface opposite the upper surface and a side face between the rear surface and the upper surface, the method comprising:
forming Group III nitride material on the upper surface and the side face of the substrate, including on a peripheral region of the upper surface that bounds an active area of the upper surface, wherein the Group III nitride material formed on the active area comprises one or more epitaxial Group III nitride layers;
depositing a first dielectric layer comprising silicon nitride onto at least a region of Group III nitride material that covers the side face of the substrate and the peripheral region of the upper surface of the substrate; and
depositing a second dielectric layer comprising silicon oxide on the first dielectric layer, the second dielectric layer covering at least the side face of the substrate and the peripheral region of the upper surface of the substrate.

11. The method of claim 10 , wherein the first dielectric layer comprises at least one of a SiN x layer, a SiO x layer and a polysilicon layer.

12. The method of claim 10 , wherein the Group III nitride material has a non-epitaxial relationship with the substrate in the peripheral region of the upper surface.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Ostermaier Clemens
• Prechtl Gerhard
• Haeberlen Oliver

Classifications

• H10P90/128 Primary

  by edge treatment, e.g. chamfering · CPC title

• H10P70/56

  Cleaning of wafer backside · CPC title

• H10P70/54

  Cleaning of wafer edges · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title