12C bus controller slave address register and command FIFO buffer

Patent metadata

Field	Value
Publication number	US-10198382-B2
Application number	US-201615091968-A
Country	US
Kind code	B2
Filing date	Apr 6, 2016
Priority date	Dec 13, 2012
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

Performing transactions on a bus by first generating a sequence of commands by an initiator module and queuing the sequence of commands in a queue module. A first one of the sequence of commands is sent from the queue module via the bus to a target module. The queue module is paused while waiting for a response via the bus from the target module; however, the initiator may continue processing another task. The queue module repeatedly sends a next command via the bus to the target module and waits for a response via the bus from the target module until a last one of the sequence of commands is sent to the target module. The queue module provides only a single acknowledgement to the initiator module after the sequence of commands has been transferred to the target module.

First claim

What is claimed is:

1. An integrated circuit I2C controller comprising:
protocol logic having a peripheral bus interface and a queue logic interface;
I2C logic having a queue logic interface and an I2C bus interface;
queue logic having a protocol logic interface coupled to the protocol logic and an I2C interface coupled to the I2C queue logic interface, the queue logic including:
a register block coupled to the protocol logic, the register block including a control register with a start bit position, a read data register, a write data register, and a slave address register having inputs coupled to the protocol logic and having outputs;
master/slave control logic coupled to the register block and to the I2C logic and having an interrupt signal output;
a command FIFO buffer having inputs coupled to the outputs of the slave address register and outputs coupled to the I2C logic, the command FIFO buffer including plural address registers to accumulate plural addresses from the slave address register at the same time; and
read and write data FIFO buffers coupled to the read data register, to the write data register, to the master/slave control logic, to the command FIFO buffer, and to the I2C logic; and
the master/slave control logic sending an interrupt signal on the interrupt signal output only after sending all of the I2C bus slave data to all of the I2C bus slave addresses.

2. The I2C controller of claim 1 in which the command FIFO buffer has five address registers.

3. The I2C controller of claim 1 including a peripheral bus coupled to the peripheral bus interface.

4. The I2C controller of claim 1 including a peripheral bus coupled to the peripheral bus interface and a local host coupled to the peripheral bus.

5. The I2C controller of claim 1 including an I2C master/slave device coupled to the I2C interface.

6. The I2C controller of claim 1 including an I2C multiplexer coupled to the I2C interface.

7. The I2C controller of claim 1 including an I2C A/D converter coupled to the I2C interface.

8. The I2C controller of claim 1 including an I2C repeater coupled to the I2C interface.

9. The I2C controller of claim 1 including an I2C bridge coupled to the I2C interface.

10. An integrated circuit bus interface controller comprising:
protocol logic having a peripheral bus interface and a first queue logic interface;
bus interface logic having a second queue logic interface and a bus interface, the bus interface having a bidirectional data line and a bidirectional clock line;
queue logic having a protocol interface coupled to the first queue logic interface and a bus logic interface coupled to the second queue logic interface, the queue logic including:
a register block coupled to the protocol interface, the register block including a control register with a start bit position, a read data register, a write data register, and a slave address register;
master/slave control logic coupled to the register block and to the bus logic interface and having an interrupt signal output;
a command FIFO buffer coupled to the slave address register and coupled to the bus logic interface, the command FIFO buffer including plural address registers to accumulate plural addresses from the slave address register at the same time; and
read and write data FIFO buffers coupled to the read data register, to the write data register, to the master/slave control logic, and to the bus logic interface; and
the master/slave control logic sending an interrupt signal on the interrupt signal output only after sending all of the I2C bus slave data to all of the I2C bus slave addresses.

11. The bus interface controller of claim 10 in which the command FIFO buffer has five address registers.

12. The bus interface controller of claim 10 including a multiplexer coupled to the bus interface.

13. The bus interface controller of claim 10 including a bridge coupled to the bus interface.

14. The bus interface controller of claim 10 including a peripheral bus coupled to the peripheral bus interface and a local host coupled to the peripheral bus.

Assignees

• Texas Instruments Inc

Inventors

• Danis Frederic
• Badi Eric Louis Pierre

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/1642

  with request queuing · CPC title

• G06F13/32 Primary

  using combination of interrupt and burst mode transfer · CPC title

• G06F13/404

  with address mapping · CPC title

• G06F13/1673

  using buffers · CPC title