Memory system including dram cache and cache management method thereof

Patent metadata

Field	Value
Publication number	US-2017192888-A1
Application number	US-201615390063-A
Country	US
Kind code	A1
Filing date	Dec 23, 2016
Priority date	Dec 30, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

A memory system includes a nonvolatile memory electrically connected to a data bus, a DRAM electrically connected to the data bus, and a memory controller configured to drive the DRAM as a cache memory and the nonvolatile memory as a main memory and to synchronize data of a cache line with data of the nonvolatile memory in units of cache units based on a dirty flag. The DRAM is configured to load data of the cache line that caches data stored in the nonvolatile memory and to store the dirty flag, which indicates whether a cache unit is dirty, in units of cache units, where a size of each cache unit is smaller than a size of the cache line.

First claim

1 . A memory system, comprising:
a nonvolatile memory electrically connected to a data bus; a dynamic random access memory (DRAM) electrically connected to the data bus, wherein the DRAM is configured to load data of a cache line that caches data stored in the nonvolatile memory and to store a dirty flag, which indicates whether a cache unit is dirty, in units of cache units, where a size of each cache unit is smaller than a size of the entire cache line; and a memory controller configured to drive the DRAM as a cache memory and the nonvolatile memory as a main memory and to synchronize data of the cache line with data of the nonvolatile memory in units of the cache units based on the dirty flag.

2 . The memory system of claim 1 , wherein the memory controller controls the DRAM and the nonvolatile memory such that the cache units each of which has the dirty flag of a dirty state are flushed to the nonvolatile memory.

3 . The memory system of claim 1 , wherein the DRAM comprises:
at least one DRAM device configured to store the data of the cache line and the dirty flag; and a cache controller configured to set the dirty flag based on an address provided from the memory controller.

4 . The memory system of claim 3 , wherein the DRAM device comprises:
a first cell region configured to store the data of the cache line; and a second cell region configured to store the dirty flag.

5 . The memory system of claim 4 , wherein the DRAM device further comprises:
a sense amplifier configured to write the dirty flag in the second cell region or to sense the written dirty flag.

6 . The memory system of claim 1 , wherein the memory controller extracts tag information included in the cache line during an operation of updating the cache line to check whether a cache hit of write requested data occurs.

7 . The memory system of claim 6 , wherein when the cache hit of the write requested data occurs, the memory controller controls the DRAM such that the cache line is updated with the write requested data and the dirty flag is set to have a dirty state.

8 . The memory system of claim 1 , wherein a size of data input to the nonvolatile memory and output from the nonvolatile memory is greater than a size of data input to the DRAM and output from the DRAM.

9 . The memory system of claim 8 , wherein a size of each of the cache units corresponds to a size of the data input to the DRAM and output from the DRAM, and a size of the cache line corresponds to the size of the data input to the nonvolatile memory and output from the nonvolatile memory.

10 . The memory system of claim 1 , wherein the nonvolatile memory comprises at least one of an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), or a spin-torque magnetic RAM (STT-MRAM).

11 . A cache management method of a memory system that comprises a nonvolatile memory and a dynamic random access memory (DRAM), the method comprising:
storing data stored in the nonvolatile memory in a cache line of the DRAM and performing a cache update operation in units of cache units constituting the cache line; storing a dirty flag indicating whether each of the cache units is in a dirty state or a clean state; reading the dirty flag to determine the dirty state of each of the cache units; reading cache units, which are detected as having the dirty state, from among the plurality of cache units from the DRAM; and flushing the read cache units to the nonvolatile memory.

12 . The method of claim 11 , wherein the DRAM inputs or outputs data with a size corresponding to a size of each cache unit, and the nonvolatile memory inputs or outputs data with a size corresponding to the cache line.

13 . The method of claim 11 , further comprising:
reading the cache line to extract tag information; and determining whether a cache hit occurs, based on the extracted tag information.

14 . The method of claim 11 , wherein the DRAM has a memory region storing the dirty flag.

15 . The method of claim 14 , wherein the DRAM comprises:
a first cell region configured to store one of the cache units; and a second cell region configured to store a dirty flag corresponding to the one cache unit.

16 . The method of claim 14 , wherein the DRAM comprises:
a plurality of DRAM devices each configured to store the cache units; and at least one DRAM device configured to store a dirty flag corresponding to each of the cache units.

17 . A memory device configured as a cache memory, the memory device comprising:
a dynamic random access memory (DRAM) comprising a first cell region configured to store cache units constituting a cache line and a second cell region configured to store a dirty flag indicating a dirty state of each of the cache units; and a cache controller configured to determine the dirty state of each of the cache units based on an address provided according to a write request from an external device and to update the second cell region based on the determined dirty state of each of the cache units.

18 . The memory device of claim 17 , wherein a size of the cache line used by the memory device to cache data corresponds to a size of a data input to a main memory or output from the main memory.

19 . The memory device of claim 18 , wherein a size of each of the cache units corresponds to a size of a data input to the memory device or output from the memory device.

20 . The memory device of claim 17 , wherein the DRAM comprises a plurality of DRAM devices constituting the first cell region and at least one DRAM device constituting the second cell region.

21 - 25 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• Moon Sungup
• Ko Tae-Kyeong
• Kim Do-Han
• Park Jongmin
• Won Kyoyeon

Classifications

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F13/4068

  Electrical coupling · CPC title