Test, validation, and debug architecture

Patent metadata

Field	Value
Publication number	US-10198333-B2
Application number	US-201013997182-A
Country	US
Kind code	B2
Filing date	Dec 23, 2010
Priority date	Dec 23, 2010
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

First claim

What is claimed is:

1. An apparatus comprising:
at least one hardware testing hook integrated within a physical layer of a device to provide test information collected from the device to a software layer, the at least one hardware testing hook to provide access to circuit traces regardless of a small form factor of the circuit and obviating use of a probe, the test information to be used for testing, validation, or debug, and relating to test events;
a power grid characterization circuit to provide temporally and spatially characterized power grid performance information correlated with the test events, the temporal characterization to occur while the device is quiescent, in a boot cycle, during a test, and during a system event, and the spatial characterization to occur in a plurality of power domains simultaneously; and
a validation control circuit comprising a microcontroller integrated within the device to control access to the at least one integrated hardware testing hook and provide an interface to the software layer, the access being either local or remote, the interface to provide services associated with the at least one integrated hardware testing hook, the services comprising at least setting a trigger scenario to occur during operation of the device, gathering the test information when the trigger scenario occurs, storing the test information to a memory, and obfuscating details of accessing the at least one integrated hardware testing hook from the software layer.

2. The apparatus of claim 1 , wherein the at least one integrated hardware testing hook captures voltages in the physical layer of the device by counting oscillations of a ring oscillator over short periods of time.

3. The apparatus of claim 1 , wherein the services further comprise at least one of:
coordinating a trigger scenario, the trigger scenario comprising a microbreakpoint trigger event;
extracting a stored trace;
delivering validation information; and
providing different levels of access.

4. The apparatus of claim 1 , wherein the validation control circuit is to provide at least one application programming interface (API) to receive a request from software.

5. The apparatus of claim 4 , wherein the validation control circuit is to determine a security level access of the request.

6. The apparatus of claim 1 , wherein obfuscating details of accessing the at least one integrated hardware testing hook from the software layer comprises storing information captured by the at least one integrated hardware testing hook in a region of memory obfuscated from view of an operating system.

7. An apparatus comprising:
a physical layer of a device comprising at least one integrated hardware testing hook to provide test information, the at least one integrated hardware testing hook to provide access to circuit traces regardless of a small form factor of the circuit and obviating use of a probe, the at least one integrated testing hook further to capture voltages in the physical layer of the device by counting oscillations of a ring oscillator over short periods of time and an on-die logic analyzer to collect trace information from the device; and
a validation control circuit to abstract the at least one integrated hardware testing hook from a software layer, control access to the physical layer, the access being either local or remote, provide an interface to a software layer, the interface to provide services associated with the at least one integrated hardware testing hook, the services comprising at least setting a trigger scenario to occur during normal operation of the device, gathering the test information when the trigger scenario occurs, and storing the test information to a memory, the validation control circuit further to conceal details of the at least one integrated hardware testing hook from the software layer.

8. The apparatus of claim 7 , wherein the validation control circuit is to provide a plurality of access levels to the software layer.

9. The apparatus of claim 7 , wherein the validation control circuit is further to store the test information in memory data structure having a predefined format.

10. A system comprising:
a processor;
a memory;
a physical layer of a device comprising at least one integrated hardware testing hook to provide test information, the at least one integrated hardware testing hook to provide access to circuit traces regardless of a small form factor of the circuit and obviating use of a probe, wherein the at least one integrated hardware testing hook captures voltages over time in the physical layer of the device by counting oscillations of a ring oscillator over short periods of time; and
a validation control circuit to abstract the at least one integrated hardware testing hook from a software layer, control access to the physical layer, the access being either local or remote, provide an interface to the software layer, the interface to provide services associated with the at least one integrated hardware testing hook, the services comprising at least setting a trigger scenario to occur during normal operation of the device, gathering the test information when the trigger scenario occurs, and storing the test information to a memory, the validation control circuit further to conceal details of the at least one integrated hardware testing hook from the software layer.

11. The system of claim 10 , wherein the on-die logic analyzer is to monitor architectural registers of the processor.

12. The system of claim 10 , wherein the on-die logic analyzer is to monitor a memory interface of the processor.

13. The system of claim 10 , wherein the on-die logic analyzer is to monitor an input/output interface of the processor.

14. The system of claim 13 , wherein the on-die logic analyzer is to validate conformance with a protocol by the processor.

15. The system of claim 10 , wherein the on-die logic analyzer is to validate an electrical attribute of the processor.

16. The system of claim 10 , wherein the on-die logic analyzer is to set a trigger event and to gather data upon occurrence of the trigger event.

17. The system of claim 16 , wherein the on-die logic analyzer is further to set a state of the processor into a test scenario before setting the trigger event.

18. The apparatus of claim 1 , wherein the trigger scenario comprises a complex combination of microarchitectural events.

19. The apparatus of claim 1 , wherein the validation control circuit performs equivalent functionality as an external logic analyzer and obviates a need to use the external logic analyzer.

20. The apparatus of claim 1 , wherein the validation control circuit is to be designed concurrently with the device and to reflect the latest features and capabilities of the device.

Assignees

• Trobough Mark B
• Tiruvallur Keshavan K
• Prudvi Chinna B
• Iovin Christian E
• Grawrock David W
• Nejedlo Jay J
• Kabadi Ashok N
• Goff Travis K
• Halprin Evan J
• Udawatta Kapila B
• Foo Jiun Long
• Cheah Wee Hoo
• Liew Vui Yong
• Gopal Selvakumar Raja
• Lee Yuen Tat
• Samaan Samie B
• Killpack Kip C
• Dobler Neil
• Hakim Nagib Z
• Meyer Brian
• Penner William H
• Baudrexl John L
• Wunderlich Russell J
• Grealish James J
• Markley Kyle
• Storey Timothy S
• Mcconnell Loren J
• Cool Lyle E
• Kataria Mukesh
• Mohammed Rahima K
• Zheng Tieyu
• Xia Yi Amy
• Sahan Ridvan A
• Ramadorai Arun R
• Patra Priyadarsan
• Parks Edwin E
• Davare Abhijit
• Gopal Padmakumar
• Querbach Bruce
• Gartler Hermann W
• Drescher Keith
• Salem Sanjay S
• Florey David C
• Intel Corp

Inventors

• Trobough Mark B
• Tiruvallur Keshavan K
• Prudvi Chinna B
• Iovin Christian E
• Grawrock David W
• Nejedlo Jay J
• Kabadi Ashok N
• Goff Travis K
• Halprin Evan J
• Udawatta Kapila B
• Foo Jiun Long
• Cheah Wee Hoo
• Liew Vui Yong
• Gopal Selvakumar Raja
• Lee Yuen Tat
• Samaan Samie B
• Killpack Kip C
• Dobler Neil
• Hakim Nagib Z
• Meyer Brian
• Penner William H
• Baudrexl John L
• Wunderlich Russell J
• Grealish James J
• Markley Kyle
• Storey Timothy S
• Mcconnell Loren J
• Cool Lyle E
• Kataria Mukesh
• Mohammed Rahima K
• Zheng Tieyu
• Xia Yi Amy
• Sahan Ridvan A
• Ramadorai Arun R
• Patra Priyadarsan
• Parks Edwin E
• Davare Abhijit
• Gopal Padmakumar
• Querbach Bruce
• Gartler Hermann W
• Drescher Keith
• Salem Sanjay S
• Florey David C

Classifications

• G06F11/2733 Primary

  Test interface between tester and unit under test · CPC title

• G06F11/267 Primary

  Reconfiguring circuits for testing, e.g. LSSD, partitioning · CPC title

• G06F11/22

  Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing · CPC title

• G06F11/36 Primary

  Prevention of errors by analysis, debugging or testing of software · CPC title

• G06F11/3648

  using additional hardware · CPC title