Information processing apparatus with debugging unit and debugging method therefor

Patent metadata

Field	Value
Publication number	US-9213615-B2
Application number	US-201514625814-A
Country	US
Kind code	B2
Filing date	Feb 19, 2015
Priority date	Feb 19, 2010
Publication date	Dec 15, 2015
Grant date	Dec 15, 2015

Abstract

An information processing apparatus includes an external tool unit configured to provide a man-machine interface to a debugging user; and a microcontroller. The microcontroller includes: a CPU section configured to execute a program as a debugging target in a response to a first clock signal, wherein a clock rate of the first clock signal is changed in response to an instruction from the CPU section; a first transmitting section configured to transmit debugging data to the external tool unit in response to the first clock signal; a second transmitting section configured to transmit the debugging data to the external tool unit in response to a second clock signal which is different from the first clock signal; and a receiving section configured to receive data transmitted from the external tool unit.

First claim

What is claimed is:

1. A microcontroller comprising:
a CPU section configured to execute a program as a debugging target in response to a first clock signal having a clock rate that is variable, wherein the clock rate of said first clock signal is changed in response to an instruction from said CPU section;
a first transmitting section configured to output debugging data in response to said first clock signal;
a second transmitting section configured to output the debugging data in response to a second clock signal, which is different from said first clock signal and has a clock rate that is fixed.

2. The microcontroller according to claim 1 , further comprising:
a sequence control section configured to select a transmitting section from among said first transmitting section and said second transmitting section in response to a command and to transmit the debugging data by using the selected transmitting section.

3. The microcontroller according to claim 2 , wherein said CPU section comprises:
a CPU configured to execute the program in response to said first clock signal; and
a clock control section configured to receive, as the instruction from the CPU, a clock rate change request for the clock rate of said first clock signal, notify said sequence control section of the clock rate change request, and change the clock rate of said first clock signal in response to receiving a permission signal from the sequence control section, and
wherein said sequence control section outputs the permission signal to said clock control section.

4. The microcontroller according to claim 1 , wherein said first clock signal is a system clock signal supplied to said CPU section, and said second clock signal is a debug clock signal with a fixed clock rate used for debugging.

Assignees

• Renesas Electronics Corp

Inventors

• Matsukawa Kazuya

Classifications

• G06F13/38 Primary

  Information transfer, e.g. on bus (G06F13/14 takes precedence) · CPC title

• G06F11/26 Primary

  Functional testing · CPC title

• G06F11/2236

  to test CPU or processors · CPC title

• G06F11/36

  Prevention of errors by analysis, debugging or testing of software · CPC title

• G06F11/2733

  Test interface between tester and unit under test · CPC title