Electronic device comprising an encapsulating block locally of smaller thickness

Patent metadata

Field	Value
Publication number	US-10186466-B2
Application number	US-201715728969-A
Country	US
Kind code	B2
Filing date	Oct 10, 2017
Priority date	Feb 26, 2016
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

An electronic device includes a carrier substrate with at least one integrated-circuit chip mounted on a front face of the carrier substrate. An encapsulation block on the front face and embedding the integrated-circuit chip has a periphery with corners. The encapsulating block further has, in at least one local zone located in at least one corner and from the front face of the carrier substrate, a smaller thickness than a thickness of the encapsulation block at least in a surrounding zone. The electronic device is manufactured by a process in which the zone of smaller thickness is obtained by molding or by machining.

First claim

The invention claimed is:

1. A process, comprising:
mounting integrated-circuit chips on adjacent locations of a front face of a carrier substrate;
placing the carrier substrate equipped with the integrated-circuit chips in a cavity of a mold, wherein the mold comprises portions protruding in a direction of the carrier substrate from a face of said cavity located facing said front face of said carrier substrate, the protruding portions extending over front zones located facing and away from adjacent corners of said adjacent locations;
injecting an encapsulating material into a space of the cavity between the carrier substrate and said face of the cavity in order to produce a common encapsulating block; and
dicing the carrier substrate and the common encapsulating block along common sides of said adjacent locations.

2. The process according to claim 1 , wherein a distance between said protruding portions and said front face of the carrier substrate is comprised between ten and fifty percent of a distance between said face of the cavity and said front face of the carrier substrate.

3. A process for simultaneously manufacturing electronic devices, comprising:
mounting integrated-circuit chips on adjacent locations of a front face of a carrier substrate;
placing the carrier substrate equipped with the integrated-circuit chips in a cavity of a mold;
injecting an encapsulating material into a space of the cavity between the carrier substrate and a face of the cavity in order to produce a common encapsulating block;
machining voids in front zones of the common encapsulating block covering adjacent corners of said adjacent locations in such a way as to leave behind a smaller thickness of the common encapsulating block; and
dicing the carrier substrate and the common encapsulating block along common sides of said adjacent locations.

4. The process according to claim 3 , wherein the smaller thickness of the common encapsulating block, in the zones of said voids, is comprised between ten and fifty percent of the thickness of this block in the surrounding zones.

Assignees

• St Microelectronics Grenoble 2

Inventors

• Besancon Benoit
• Petit Luc

Classifications

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W72/0198

  batch processes · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/016

  using moulds · CPC title