Method for manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-10181401-B1
Application number	US-201815865227-A
Country	US
Kind code	B1
Filing date	Jan 8, 2018
Priority date	Jan 8, 2018
Publication date	Jan 15, 2019
Grant date	Jan 15, 2019

Abstract

A method for manufacturing a semiconductor device includes: forming a first patterned target layer on a substrate having a first region and a second region, the first patterned target layer having first openings along a first direction in the first region; forming a patterned hard mask layer over the first patterned target layer and having first recesses along a second direction in the first region and second recesses along the first direction in the second region; forming a patterned photoresist layer over the patterned hard mask layer and having stripe structures along the second direction in the first region and block structures along the first direction in the second region; and etching the patterned photoresist layer, patterned hard mask layer, and first patterned target layer to form a second patterned target layer.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising following operations:
forming a first patterned target layer on a substrate having a first region and a second region, wherein the first patterned target layer has a plurality of first openings along a first direction in the first region, the first openings expose a portion of the substrate;
forming a patterned hard mask layer over the first patterned target layer, wherein the patterned hard mask layer has a plurality of first recesses along a second direction in the first region and a plurality of second recesses along the first direction thereon in the second region;
forming a patterned photoresist layer over the patterned hard mask layer, wherein the patterned photoresist layer has a plurality of stripe structures along the second direction in the first region and a plurality of block structures along the first direction in the second region; and
etching the patterned photoresist layer, the patterned hard mask layer, and the first patterned target layer by using the patterned hard mask layer and the patterned photoresist layer as etching masks to form a second patterned target layer.

2. The method of claim 1 , wherein a width of each stripe structure is smaller than a width of each first recess, a width of each block structure is smaller than a width of each second recess, each of the stripe structures overlaps a part of a corresponding one of the first recesses, and each of the block structures overlaps a part of a corresponding one of the second recesses.

3. The method of claim 1 , wherein a plurality of geometries of a top-viewing profile of the second patterned target layer in the first region are rhomboidal.

4. The method of claim 1 , wherein a plurality of geometries of a top-viewing profile of the second patterned target layer in the first region are rectangular.

5. The method of claim 1 , wherein the operation of forming the first patterned target layer on the substrate further comprises following operations:
forming a target layer, a lower hard mask layer, and a first upper hard mask layer in sequence on the substrate;
patterning the first upper hard mask layer to form a patterned first upper hard mask layer on the lower hard mask layer, wherein the patterned first upper hard mask layer has a plurality of second openings exposing portions of the lower hard mask layer;
conformally forming a spacer layer on top surfaces and sidewalls of the patterned first upper hard mask layer and top surfaces of the exposed portions of the lower hard mask layer;
etching the spacer layer to form a patterned spacer layer, wherein the patterned spacer layer includes a plurality of spacers located on the sidewalls of the patterned first upper hard mask layer, sidewalls of the adjacent spacers are spaced from each other by a third opening in the first region;
filling the third opening with a material the same as the patterned first upper hard mask layer to form a second upper hard mask layer, wherein top surfaces of the spacers of the patterned spacer layer are exposed out of the second upper hard mask layer;
etching the spacers of the patterned spacer layer and the lower hard mask layer by using the second upper hard mask layer as an etching mask to form a patterned lower hard mask layer; and
etching the second upper hard mask layer, the patterned lower hard mask layer, and the target layer to form the first patterned target layer.

6. The method of claim 5 , wherein the operations of etching the spacer layer, etching the spacers of the patterned spacer layer and the lower hard mask layer, and etching the second upper hard mask layer, the patterned lower hard mask layer, and the target layer are performed by anisotropic etching processes.

7. The method of claim 5 , wherein the lower hard mask layer has a plurality of layers made of different material.

8. The method of claim 5 , wherein the spacer layer and the first upper hard mask layer are made of different material.

9. The method of claim 8 , wherein the spacer layer and the first upper hard mask layer comprise Si, SiN, SiCN or SiO 2 .

10. The method of claim 1 , wherein the operation of etching the patterned photoresist layer, the patterned hard mask layer, and the first patterned target layer is performed by anisotropic etching processes.

11. The method of claim 1 , wherein the patterned hard mask layer has a plurality of layers made of different materials.

Assignees

• Nanya Technology Corp

Inventors

• Shih Shing-Yih

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P50/287

  by chemical means · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title