Intelligent memory architecture for increased efficiency

Patent metadata

Field	Value
Publication number	US-10180803-B2
Application number	US-201514810895-A
Country	US
Kind code	B2
Filing date	Jul 28, 2015
Priority date	Jul 28, 2015
Publication date	Jan 15, 2019
Grant date	Jan 15, 2019

Abstract

A method includes receiving a first request, from a first master core, to access data in one of a plurality of memory banks. It is determined whether an access to the data is stalled by virtue of a second request, from a second master core, to access the data in the one of the plurality of memory banks, the second request currently being serviced. In response to a determination that the access to the requested data is stalled, the first request is serviced by accessing data in one of a plurality of coding banks, each coding bank smaller in size than each memory bank.

First claim

What is claimed is:

1. A system comprising:
a plurality of master core processors;
a plurality of memory banks;
one or more coding banks, each of the one or more coding banks being smaller than each of the plurality of memory banks;
a plurality of bank queues that queue requests for the memory banks;
an arbiter coupled between the master core processors and the bank queues to receive requests from the master core processors and provide the requests to the bank queues; and
an access scheduler coupled between the bank queues, the memory banks, and the one or more coding banks to process the requests such that a conflicting request serviceable by the one or more coding banks is provided to the one or more coding banks,

wherein data in the one or more coding banks is coded such that servicing a first request includes decoding the data by obtaining at least one other piece of data from the memory banks and using the at least one other piece of data to decode the data.

2. The system of claim 1 , wherein coded data in the one of the coding banks is coded via an Exclusive OR (XOR) operation.

3. The system of claim 1 , wherein the system is located in a wireless base station.

4. The system of claim 3 , wherein the wireless base station is a Long-Term Evolution (LTE) base station.

5. A system comprising:
a plurality of master core processors;
a plurality of memory banks;
one or more coding banks, each of the one or more coding banks being smaller than each of the plurality of memory banks;
a plurality of bank queues that queue requests for the memory banks;
an arbiter coupled between the master core processors and the bank queues to receive requests from the master core processors and provide the requests to the bank queues; and
an access scheduler coupled between the bank queues, the memory banks, and the one or more coding banks to process the requests such that a conflicting request serviceable by the one or more coding banks is provided to the one or more coding banks,

wherein the arbiter is configured to load data in the one or more coding banks using a lookahead process on requests stored in the bank queues.

6. The system of claim 5 , wherein the arbiter is further configured to fill and update codes for writes via a background process.

7. A system comprising:
a plurality of master core processors;
a plurality of memory banks;
one or more coding banks, each of the one or more coding banks being smaller than each of the plurality of memory banks;
a plurality of bank queues that queue requests for the memory banks;
an arbiter coupled between the master core processors and the bank queues to receive requests from the master core processors and provide the requests to the bank queues; and
an access scheduler coupled between the bank queues, the memory banks, and the one or more coding banks to process the requests such that a conflicting request serviceable by the one or more coding banks is provided to the one or more coding banks,
wherein the processing the requests include processing the requests in parallel to allow parallel access to information from a memory bank via a plurality of coding banks, and wherein data is coded in the coding banks using an interbank coding means.

8. A system comprising:
a plurality of master core processors;
a plurality of memory banks;
one or more coding banks, each of the one or more coding banks being smaller than each of the plurality of memory banks;
a plurality of bank queues that queue requests for the memory banks;
an arbiter coupled between the master core processors and the bank queues to receive requests from the master core processors and provide the requests to the bank queues; and
an access scheduler coupled between the bank queues, the memory banks, and the one or more coding banks to process the requests such that a conflicting request serviceable by the one or more coding banks is provided to the one or more coding banks,

wherein the processing the requests include processing the requests in parallel to allow parallel access to information from a memory bank via a plurality of coding banks, and wherein data is coded in the coding banks using an intrabank coding means.

9. A system comprising:
a plurality of master core processors;
a plurality of memory banks;
one or more coding banks, each of the one or more coding banks being smaller than each of the plurality of memory banks;
a plurality of bank queues that queue requests for the memory banks;
an arbiter coupled between the master core processors and the bank queues to receive requests from the master core processors and provide the requests to the bank queues; and
an access scheduler coupled between the bank queues, the memory banks, and the one or more coding banks to process the requests such that a conflicting request serviceable by the one or more coding banks is provided to the one or more coding banks,

wherein the processing the requests include processing the requests in parallel to allow parallel access to information from a memory bank via a plurality of coding banks, and wherein data is coded in the coding banks using a combination of an intrabank coding means and an interbank coding means.

Assignees

• Futurewei Technologies Inc

Inventors

• Luan Hao
• Gatherer Alan
• Vishwanath Sriram
• Hunger Casen
• Jain Hardik

Classifications

• G06F3/0611

  in relation to response time · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0622 Primary

  in relation to access · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title