Dynamic coding algorithm for intelligent coded memory system

US2017031606A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2017031606-A1
Application numberUS-201514811357-A
CountryUS
Kind codeA1
Filing dateJul 28, 2015
Priority dateJul 28, 2015
Publication dateFeb 2, 2017
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Systems and techniques for dynamic coding of memory regions are described. A described technique includes monitoring accesses to a group of memory regions, each region including two or more portions of a group of data banks; detecting a high-access memory region based on whether accesses to a region of the group of memory regions exceeds a threshold; generating coding values of a coding region corresponding to the high-access memory region, the high-access memory region including data values distributed across the group of banks; and storing the coding values of the coding region in a coding bank.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method comprising: monitoring accesses to a group of memory regions, each region comprising two or more portions of a group of data banks; detecting a high-access memory region based on whether accesses to a region of the group of memory regions exceeds a threshold; generating coding values of a coding region corresponding to the high-access memory region, the high-access memory region comprising data values distributed across the group of data banks; and storing the coding values of the coding region in a coding bank. 2 . The method of claim 1 , wherein the group of data banks comprises a first data bank and a second data bank, wherein the high-access region comprises a first portion of the first data bank and a second portion of the second data bank, wherein the coding bank is smaller than the first data bank, and wherein generating the coding values comprises generating pairs of data values, each pair comprising a data value from the first portion and a data value from the second portion. 3 . The method of claim 1 , comprising: using the coding bank to increase a number of parallel memory accesses to the high-access memory region that are serviceable in a single cycle from a first number of accesses to a second, greater number of memory accesses. 4 . The method of claim 1 , comprising: evicting a coding region within the coding bank, wherein storing the coding values in the coding bank comprises storing the storing the coding values in the evicted coding region. 5 . The method of claim 1 , comprising: receiving a first memory request to a first data bank of the group of data banks; receiving a second memory request to a second data bank of the group of data banks; determining whether the second request is satisfiable based on data produced by the first memory request and a coding value from the coding bank; and scheduling, in a single cycle, accesses comprising (i) an access for data from the first data bank to satisfy the first memory request and (ii) an access for data from the coding bank in lieu of the second data bank to satisfy the second memory request. 6 . The method of claim 5 , comprising: reconstructing data based on the data from the first data bank and the data from the coding bank; and providing the reconstructed data in response to the second memory request. 7 . The method of claim 1 , comprising: detecting a bank conflict among memory requests to a first data bank of the group of data banks, the memory requests comprising a first memory request and a second memory request; determining a second data bank of the group of data banks based on the second memory request and a coding configuration of the coding bank; accessing, in a cycle, the first data bank to satisfy the first memory request; accessing, in the cycle, the second data bank and the coding bank in lieu of the first data bank to satisfy the second memory request; reconstructing data based on data from the second data bank and the coding bank; and providing the reconstructed data in response to the second memory request. 8 . The method of claim 7 , wherein the coding configuration specifies two or more coding groupings, each coding group covering at least two banks within the group of data banks. 9 . The method of claim 1 , comprising: detecting a bank conflict among a group of memory requests to a first data bank of the group of data banks; determining whether a coding region exists in the coding bank that corresponds to a memory region associated with the bank conflict; and using a coding based alternate memory access technique to resolve the bank conflict by diverting at least one of the memory requests to an alternate data bank and the coding region. 10 . A system comprising: a group of data banks; coding bank; and a memory controller coupled with the group of data banks and the coding bank, wherein the memory controller is configured to (i) monitor accesses to a group of memory regions, each region representing a different portion of the data banks, (ii) detect a high-access memory region based on whether accesses to a region of the group of memory regions exceeds a threshold, (iii) generate coding values of a coding region corresponding to the high-access memory region, the high-access memory region comprising data values distributed across the group of data banks, and (iv) store the coding values of the coding region in the coding bank. 11 . The system of claim 10 , wherein the group of data banks comprises a first data bank and a second data bank, wherein the high-access region comprises a first portion of the first data bank and a second portion of the second data bank, wherein the coding bank is smaller than the first data bank, and wherein the memory controller is configured to generate pairs of data values, each pair comprising a data value from the first portion and a data value from the second portion. 12 . The system of claim 10 , wherein the memory controller is configured to use the coding bank to increase a number of parallel memory accesses to the high-access memory region that are serviceable in a single cycle from a first number of accesses to a second, greater number of memory accesses. 13 . The system of claim 10 , wherein the memory controller is configured to evict a coding region within the coding bank to produce an evicted coding region, wherein the coding values are stored in the evicted coding region. 14 . The system of claim 10 , wherein the memory controller is configured to receive a first memory request to a first data bank of the group of data banks, receive a second memory request to a second data bank of the group of data banks, determine whether the second request is satisfiable based on data produced by the first memory request and a coding value from the coding bank, and schedule, in a single cycle, accesses comprising (i) an access for data from the first data bank to satisfy the first memory request and (ii) an access for data from the coding bank in lieu of the second data bank to satisfy the second memory request. 15 . The system of claim 14 , wherein the memory controller is configured to reconstruct data based on the data from the first data bank and the data from the coding bank to produce reconstructed data, and provide the reconstructed data in response to the second memory request. 16 . The system of claim 10 , wherein the memory controller is configured to detect a bank conflict among memory requests to a first data bank of the group of data banks, the memory requests comprising a first memory request and a second memory request, determine a second data bank of the group of data banks based on the second memory request and a coding configuration of the coding bank, access, in a cycle, the first data bank to satisfy the first memory request, access, in the cycle, the second data bank and the coding bank in lieu of the first data bank to satisfy the second memory request, reconstruct data based on data from the second data bank and the coding bank to produce reconstructed data, and provide the reconstructed data in response to the second memory request. 17 . The system of claim 10 , wherein the memory controller is configured to detect a bank conflict among a group of memory requests to a first data bank of the group of data banks; determine whether a coding region exists in the coding bank that corresponds to a memory region associated with the bank conflict; and use a coding based alternate memory access technique to resolve the bank co

Assignees

Inventors

Classifications

  • Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163) · CPC title

  • G06F3/0611Primary

    in relation to response time · CPC title

  • Monitoring storage devices or systems · CPC title

  • Single storage device · CPC title

  • using replacement algorithms · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2017031606A1 cover?
Systems and techniques for dynamic coding of memory regions are described. A described technique includes monitoring accesses to a group of memory regions, each region including two or more portions of a group of data banks; detecting a high-access memory region based on whether accesses to a region of the group of memory regions exceeds a threshold; generating coding values of a coding region …
Who is the assignee on this patent?
Futurewei Technologies Inc
What technology area does this patent fall under?
Primary CPC classification G06F12/0284. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Feb 02 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).