Intelligent Coded Memory Architecture with Enhanced Access Scheduler

Patent metadata

Field	Value
Publication number	US-2017153824-A1
Application number	US-201514955966-A
Country	US
Kind code	A1
Filing date	Dec 1, 2015
Priority date	Dec 1, 2015
Publication date	Jun 1, 2017
Grant date	—

Abstract

A method, system, and architecture for efficiently accessing data in a memory shared by multiple processor cores that reduces the probability of bank conflicts and decreases latency is provided. In an embodiment, a method for accessing data in a memory includes determining, by a scheduler, a read pattern for reading data from memory to serve requests in a plurality of bank queues, the memory comprising a plurality of memory banks and a plurality of coding banks, the coding banks storing a coded version of at least some of the data stored in the plurality of memory banks; reading a first data from a first memory bank; reading coded data from one of the coding banks; and determining the second data according to the coded data and the first data.

First claim

What is claimed is:

1 . A method for accessing data in a memory, comprising:
determining, by a scheduler, a read pattern for reading data from memory to serve requests in a plurality of read bank queues, the memory comprising a plurality of memory banks and a plurality of coding banks, the coding banks storing a coded version of at least a portion of the data stored in the plurality of memory banks; reading, by the scheduler, a first data from a first memory bank; reading, by the scheduler, coded data from one of the coding banks; and determining, by the scheduler, second data according to the coded data and the first data.

2 . The method of claim 1 , wherein reading the first data from the first memory bank and reading the coded data from one of the coding banks are performed in parallel.

3 . The method of claim 1 , wherein the requests in the plurality of read bank queues are read in a different order from an order of the requests in the plurality of read bank queues.

4 . The method of claim 1 , further comprising:
selecting a first element and a second element from a write bank queue; writing the first element to a memory bank; and writing the second element to a coding bank as a coded memory element.

5 . The method of claim 4 , further comprising:
updating a status memory according to the writing the first element and the writing the second element, the status memory denoting a status of a code for a section of the memory bank, the status indicating whether the codes in the coding bank are up to date with the data in the memory bank, whether the codes are outdated and the data in the memory bank is current, or whether the codes are outdated and data in the coding bank is current.

6 . The method of claim 4 , further comprising:
scheduling more reads per cycle than writes per cycle.

7 . The method of claim 4 , further comprising:
scheduling a write to memory only when the write bank queue is full or when a threshold is satisfied.

8 . The method of claim 4 , wherein the threshold is different for different write bank queues.

9 . The method of claim 1 , wherein forming the read pattern comprises:
determining a first read request from a first bank queue; scheduling the first read request to be read from one of the memory banks; and searching a second bank queue to determine whether any read requests from the second bank queue can be served from one of the coding banks using a read for the first read request.

10 . The method of claim 9 , wherein the first read request is determined according to the size of the bank queues.

11 . A method in one or more master processors for accessing data in a memory, comprising:
selecting a first element and a second element from a write bank queue; writing the first element to a memory bank; and writing the second element to a coding bank as a coded memory element, writing the first element to the memory bank performed in parallel with the writing the second element to the coding bank.

12 . A data processing system, comprising:
one or more master processors; and a non-transitory computer readable storage medium storing programming for execution by the processor, the programming including instructions to:
determine a read pattern for reading data from memory to serve requests in a plurality of read bank queues, the memory comprising a plurality of memory banks and a plurality of coding banks, the coding banks storing a coded version of at least some of the data stored in the plurality of memory banks;
read a first data from a first memory bank;
read coded data from one of the coding banks; and
determine the second data according to the coded data and the first data.

13 . The data processing system of claim 12 , wherein the instructions to read the first data from the first memory bank and the instructions to read the coded data from one of the coding banks are performed in parallel.

14 . The data processing system of claim 12 , wherein the requests in the plurality of read bank queues are read in a different order from an order of the requests in the plurality of read bank queues.

15 . The data processing system of claim 12 , wherein the programing further comprises instructions to:
select a first element and a second element from a write bank queue; write the first element to a memory bank; and write the second element to a coding bank as a coded memory element.

16 . The data processing system of claim 15 , wherein the programming further comprises instructions to:
update a status memory according to the writing the first element and the writing the second element, the status memory denoting a status of a code for a section of the memory bank, the status indicating whether the codes in the coding bank are up to date with the data in the memory bank, whether the codes are outdated and the data in the memory bank is current, or whether the codes are outdated and data in the coding bank is current.

17 . The data processing system of claim 15 , wherein the programming further comprises instructions to:
schedule more reads per cycle than writes per cycle.

18 . The data processing system of claim 15 , wherein the programming further comprises instructions to:
schedule a write to memory only when the write bank queue is full.

19 . The data processing system of claim 12 , wherein the instructions to form the read pattern comprises instructions to:
determine a first read request from a first bank queue; schedule the first read request to be read from one of the memory banks; and search a second bank queue to determine whether any read requests from the second bank queue can be served from one of the coding banks using a read for the first read request.

20 . The data processing system of claim 19 , wherein the first read request is determined according to the size of the bank queues.

21 . A processor, comprising:
a plurality of master core processors; a coded memory controller; and a memory comprising a plurality of memory banks and a plurality of coding banks, the coding banks comprising coded data of at least a part of the data in the memory banks, wherein the coded memory controller comprises a plurality of bank queues and an access scheduler, wherein the bank queues comprise a list of read requests and write requests; wherein the access scheduler searches the bank queues and schedules read operations from the memory such that a read operation from a memory bank corresponding to a first read request enables obtaining data from one of the coding banks that satisfies a second read request, and wherein the access scheduler obtains two entries from a write bank queue and writes a first entry to one of the memory banks and writes a second entry to one of the coding banks as a coded data entry.

22 . The processor of claim 21 , further comprising a status memory maintained by the access scheduler, wherein the status memory indicates whether data in a memory bank and a coding bank are up to date.

23 . The processor of claim 22 , wherein the status of a memory location stored in the status memory indicates one of three statuses, wherein the three statuses include (1) the data in the memory bank and the data in the coding bank for a corresponding memory location are both up to date, (2) only the data in the memory bank for the corresponding memory location is up to date, and (3) only the data in the coding bank for the corresponding m

Assignees

• Futurewei Technologies Inc

Inventors

• Luan Hao
• Gatherer Alan
• Vishwanath Sriram
• Hunger Casen
• Jain Hardik

Classifications

• G06F11/108

  Parity data distribution in semiconductor storages, e.g. in SSD · CPC title

• G06F13/1642

  with request queuing · CPC title

• G06F13/161 Primary

  with latency improvement · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title