Electronic sensors with sensor die in package structure cavity

Patent metadata

Field	Value
Publication number	US-10179730-B2
Application number	US-201615372565-A
Country	US
Kind code	B2
Filing date	Dec 8, 2016
Priority date	Dec 8, 2016
Publication date	Jan 15, 2019
Grant date	Jan 15, 2019

Abstract

Disclosed examples include sensor apparatus and integrated circuits having a package structure with an internal cavity and an opening that connects of the cavity with an ambient condition of an exterior of the package structure, and an electronic sensor structure mechanically supported by wires in the cavity and including a sensing surface exposed to the cavity to sense the ambient condition of an exterior of the package structure.

First claim

The following is claimed:

1. An integrated circuit (IC), comprising:
a leadframe structure, including a plurality of electrical conductors;
a plurality of bond wires connected to respective ones of the electrical conductors of the leadframe structure;
a molded package structure enclosing at least portions of the leadframe structure and at least portions of the bond wires, the molded package structure including: a cavity defined by an interior surface of the molded package structure, and an opening that connects the cavity with an exterior of the IC; and
a semiconductor die disposed at least partially within the cavity, at least a portion of an outer surface of the semiconductor die being spaced from the interior surface of the molded package structure, the semiconductor die including: a sensor circuit; and a plurality of bond pads connected to respective ones of the bond wires;
the sensor circuit including: a first resistor structure unexposed to the cavity; a second resistor structure exposed to the cavity and connected in a bridge circuit with the first resistor structure; an excitation source to provide a bias signal to the bridge circuit; and an amplifier, including an input connected to the bridge circuit, and an output to provide an output signal representing relative resistances of the first and second resistor structures.

2. The IC of claim 1 , wherein all of the outer surface of the semiconductor die is spaced from the interior surface of the molded package structure.

3. The IC of claim 1 , wherein the sensor circuit further comprises a die attach structure extending between the leadframe structure and a portion of a bottom side of the semiconductor die proximate a lateral edge of the semiconductor die.

4. The IC of claim 1 , wherein the sensor circuit further comprises a thermal control circuit to control a temperature of the first resistor structure.

5. The IC of claim 4 , wherein the thermal control circuit includes:
a first conductive structure disposed proximate the first resistor structure;
a thermo-electric structure electrically connected to the first conductive structure; and
a driver to provide a current or voltage signal to the thermo-electric structure to selectively provide heat to, or remove heat from, the first conductive structure.

6. The IC of claim 5 , wherein the thermal control circuit further comprises a thermal sensing component to sense a temperature of the first conductive structure and to provide a first signal to the driver, and wherein the driver controls the current or voltage signal according to the first signal and a setpoint signal to regulate the temperature of the first resistor structure.

7. The IC of claim 6 , wherein the thermal control circuit further comprises:
a semiconductor substrate;
a dielectric layer formed on a first side of the semiconductor substrate; and
a plurality of annular conductive structures laterally outwardly spaced from one another on a first side of the dielectric layer, including an inner annular conductive structure electrically connected to the first conductive structure and an outer annular conductive structure electrically connected to at least one of the bond pads;
wherein the thermo-electric structure is formed over portions of the first side of the dielectric layer between the annular conductive structures to transfer heat in stages between the first conductive structure and the at least one bond pad.

8. The IC of claim 4 , further comprising a first passivation layer formed between the first resistor structure and the cavity.

9. The IC of claim 8 , wherein at least a portion of the second resistor structure is uncovered in the cavity.

10. The IC of claim 8 , further comprising a second passivation layer formed between the second resistor structure and the cavity, wherein the second passivation layer is thinner than the first passivation layer.

11. An integrated circuit (IC), comprising:
a leadframe structure, including a plurality of electrical conductors;
a plurality of bond wires connected to respective ones of the electrical conductors of the leadframe structure;
a molded package structure enclosing at least portions of the leadframe structure and at least portions of the bond wires, the molded package structure including: a cavity defined by an interior surface of the molded package structure, and an opening that connects the cavity with an exterior of the IC; and
a semiconductor die disposed at least partially within the cavity, at least a portion of an outer surface of the semiconductor die being spaced from the interior surface of the molded package structure, the semiconductor die including: a plurality of bond pads connected to respective ones of the bond wires; a first semiconductor substrate having first and second opposite sides; a first dielectric layer on a portion of the first side of the first semiconductor substrate; a second semiconductor substrate having first and second opposite sides, including an annular portion and an inner portion laterally inwardly spaced from the annular portion, at least a portion of the second side of the annular portion being in contact with the first dielectric layer; and a second dielectric layer on the first side of the second semiconductor substrate;
the inner portion of the second semiconductor substrate being spaced from the first semiconductor substrate by a void to form a pressure sensor diaphragm laterally inwardly spaced from the annular portion.

12. The IC of claim 11 , wherein all of the outer surface of the semiconductor die is spaced from the interior surface of the molded package structure.

Assignees

• Texas Instruments Inc

Inventors

• Male Barry Jon
• Cook Benjamin
• Neidorff Robert Alan
• Kummerl Steve

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• B81B7/0048 Primary

  between the MEMS die and the substrate · CPC title

• B81C1/00325

  for reducing stress inside of the package structure · CPC title