Methods of fabricating magnetic memory devices

Patent metadata

Field	Value
Publication number	US-10177307-B2
Application number	US-201715474388-A
Country	US
Kind code	B2
Filing date	Mar 30, 2017
Priority date	Sep 6, 2016
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

Disclosed is a method of fabricating a magnetic memory device. The method of a fabricating a magnetic memory device includes forming an interlayer dielectric layer on a substrate, forming a sacrificial pattern in the interlayer dielectric layer, forming a magnetic tunnel junction pattern on the sacrificial pattern, after forming the magnetic tunnel junction pattern, selectively removing the sacrificial pattern to form a bottom contact region in the interlayer dielectric layer, and forming a bottom contact in the bottom contact region.

First claim

What is claimed is:

1. A method of fabricating a magnetic memory device, the method comprising:
forming an interlayer dielectric layer on a substrate;
forming a sacrificial pattern in the interlayer dielectric layer;
forming a magnetic tunnel junction pattern on the sacrificial pattern;
after forming the magnetic tunnel junction pattern, selectively removing the sacrificial pattern to form a bottom contact region in the interlayer dielectric layer; and
forming a bottom contact in the bottom contact region.

2. The method of claim 1 , further comprising, before selectively removing the sacrificial pattern, forming a capping pattern covering the magnetic tunnel junction pattern,
wherein the capping pattern partially exposes the sacrificial pattern.

3. The method of claim 1 , wherein, as viewed in plan view, a portion of the magnetic tunnel junction pattern overlaps the sacrificial pattern, and another portion of the magnetic tunnel junction pattern overlaps the interlayer dielectric layer.

4. The method of claim 1 , wherein forming the magnetic tunnel junction pattern comprises:
forming a magnetic tunnel junction layer on the interlayer dielectric layer and the sacrificial pattern; and
patterning the magnetic tunnel junction layer,
wherein the sacrificial pattern is partially exposed by the patterning of the magnetic tunnel junction layer.

5. The method of claim 1 , wherein the sacrificial pattern comprises an insulating material.

6. The method of claim 5 , wherein the sacrificial pattern has an etch selectivity with respect to the interlayer dielectric layer.

7. The method of claim 5 , wherein the interlayer dielectric layer includes silicon oxide and the sacrificial pattern includes silicon nitride.

8. The method of claim 5 , wherein the interlayer dielectric layer includes silicon nitride and the sacrificial pattern includes silicon oxide.

9. A method of fabricating a magnetic memory device, the method comprising:
providing a substrate including a first region and a second region that are adjacent to each other along a first direction;
forming a first interlayer dielectric layer on the substrate;
forming a sacrificial pattern in the first interlayer dielectric layer, the sacrificial pattern extending from the first region onto the second region along the first direction;
forming magnetic tunnel junction patterns on the sacrificial pattern on the first region, the magnetic tunnel junction patterns being arranged along the first direction;
after forming the magnetic tunnel junction patterns, selectively removing the sacrificial pattern to form a bottom contact region in the first interlayer dielectric layer on the first region; and
forming a preliminary bottom contact filling the bottom contact region.

10. The method of claim 9 , further comprising, before selectively removing the sacrificial pattern, forming a capping pattern covering the magnetic tunnel junction patterns,
wherein, as viewed in a plan view, the capping pattern exposes the sacrificial pattern on the second region.

11. The method of claim 10 , further comprising patterning the preliminary bottom contact to form bottom contacts spaced apart from each other in the first direction.

12. The method of claim 11 , wherein the patterning of the preliminary bottom contact separates the capping patterns into sub-capping patterns spaced apart from each other in the first direction.

13. The method of claim 9 , further comprising patterning the preliminary bottom contact to form bottom contacts spaced apart from each other in the first direction,
wherein each of the bottom contacts is electrically connected to its corresponding one of the magnetic tunnel junction patterns.

14. The method of claim 13 , further comprising forming a second interlayer dielectric layer covering the magnetic tunnel junction patterns,
wherein air gaps are formed between the bottom contacts and below the second interlayer dielectric layer.

15. The method of claim 9 , wherein, as viewed in a plan view, a portion of each of the magnetic tunnel junction patterns overlaps the sacrificial pattern, and another portion of each of the magnetic tunnel junction patterns overlaps the first interlayer dielectric layer.

16. The method of claim 9 , wherein each of the magnetic tunnel junction patterns has a first width in a second direction perpendicular to the first direction, and the sacrificial pattern has a second width in the second direction, the first width being greater than the second width.

17. The method of claim 9 , wherein the sacrificial pattern includes a lower portion having a lower width in a second direction perpendicular to the first direction and an upper portion having an upper width in the second direction, the lower width being greater than the upper width.

18. A method of fabricating a magnetic memory device, the method comprising:
providing a substrate including a first region and a second region that are adjacent to each other along a first direction;
forming a first interlayer dielectric layer on the substrate;
forming a sacrificial pattern in the first interlayer dielectric layer, the sacrificial pattern extending from the first region onto the second region along the first direction;
forming a magnetic structure on the sacrificial pattern on the first region;
after forming the magnetic structure, selectively removing the sacrificial pattern to form a bottom contact region in the first interlayer dielectric layer on the first region; and
forming a bottom contact filling the bottom contact region.

19. The method of claim 18 , wherein forming the magnetic structure comprises sequentially depositing on the sacrificial pattern on the first region a bottom electrode layer, a magnetic tunnel junction layer, and a top electrode layer.

20. The method of claim 18 , wherein forming the magnetic structure comprises sequentially depositing on the sacrificial pattern on the first region a bottom electrode layer, a first magnetic layer, a tunnel barrier layer, a second magnetic layer, and a top electrode layer.

Assignees

• Bak Junghoon
• Son Myoungsu
• Seo Boyoung
• Samsung Electronics Co Ltd

Inventors

• Bak Junghoon
• Son Myoungsu
• Seo Boyoung

Classifications

• H01L27/222

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• G11C2211/5615

  Multilevel magnetic memory cell using non-magnetic non-conducting interlayer, e.g. MTJ · CPC title

• H01L29/82

  Electricity · mapped topic

• G11C14/0036

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title