Methods of manufacturing a magnetoresistive random access memory device

Patent metadata

Field	Value
Publication number	US-9306156-B2
Application number	US-201414533084-A
Country	US
Kind code	B2
Filing date	Nov 4, 2014
Priority date	Feb 18, 2014
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

In a method of manufacturing an MRAM device, a first sacrificial layer, an etch stop layer, and a second sacrificial layer are sequentially formed on a substrate and then partially etched to form openings therethrough. Lower electrodes are formed to fill the openings. The first and second sacrificial layers and portions of the etch stop layer are removed to form etch stop layer patterns surrounding upper portions of sidewalls of the lower electrodes, respectively. An upper insulating layer pattern is formed between the etch stop layer patterns to partially define an air pad between the lower electrodes. A first magnetic layer, a tunnel barrier layer, a second magnetic layer, and an upper electrode layer are formed, and are etched to form a plurality of magnetic tunnel junction (MTJ) structures. Each MTJ structure includes a sequentially stacked first magnetic layer pattern, tunnel layer pattern, and second magnetic layer pattern, and each of the MTJ structures contacts a corresponding one of the lower electrodes.

First claim

What is claimed is:

1. A method of manufacturing an MRAM device, the method comprising:
sequentially forming a first sacrificial layer, an etch stop layer, and a second sacrificial layer on a substrate;
partially etching the second sacrificial layer, the etch stop layer and the first sacrificial layer to form a plurality of openings therethrough;
forming a plurality of lower electrodes filling the openings;
removing the first and second sacrificial layers and portions of the etch stop layer to form etch stop layer patterns surrounding upper portions of sidewalls of the lower electrodes;
forming an upper insulating layer pattern between the etch stop layer patterns to partially define a plurality of air pads arranged between adjacent ones of the lower electrodes;
forming a first magnetic layer, a tunnel barrier layer, a second magnetic layer, and an upper electrode layer on the lower electrodes, the etch stop layer patterns, and the upper insulating layer pattern; and
etching portions of the upper electrode layer, the second magnetic layer, the tunnel barrier layer, the first magnetic layer, the upper insulating layer pattern, and the etch stop layer patterns to form a plurality of magnetic tunnel junction (MTJ) structures,
wherein each MTJ structure comprises sequentially stacked layer patterns including a first magnetic layer pattern, a tunnel layer pattern, and a second magnetic layer pattern, and wherein each MTJ structure contacts a respective one of the lower electrodes.

2. The method of claim 1 , wherein the first and second sacrificial layer are formed to include silicon oxide, and wherein the etch stop layer is formed to include silicon nitride.

3. The method of claim 1 , wherein forming lower electrodes filling the openings includes:
forming a lower electrode layer on the second sacrificial layer to fill the openings; and
polishing the lower electrode layer until an upper surface of the second sacrificial layer is exposed.

4. The method of claim 1 , wherein removing the first and second sacrificial layers and portions of the etch stop layer to form the etch stop layer patterns includes:
removing the second sacrificial layer to expose the etch stop layer;
etching portions of the etch stop layer to form the etch stop layer patterns exposing portions of the first sacrificial layer therebetween; and
removing the exposed portions of the first sacrificial layer.

5. The method of claim 1 , wherein forming the etch stop layer patterns includes:
forming capping spacers comprising an insulating material on sidewalls of the lower electrodes, said capping spacers protruding from the etch stop layer; and
etching portions of the etch stop layer between the capping spacers.

6. The method of claim 5 , wherein the capping spacers and the etch stop layer are formed including substantially the same material.

7. The method of claim 5 , wherein forming the capping spacers includes:
forming a spacer layer on sidewalls of the lower electrodes and the etch stop layer using a chemical vapor deposition (CVD) process; and
anisotropically etching the spacer layer.

8. The method of claim 5 , wherein removing the second sacrificial layer further includes removing the capping spacers.

9. The method of claim 1 , wherein forming the upper insulating layer pattern between the etch stop layer patterns includes:
forming an upper insulating layer to cover the lower electrodes and a space between the etch stop layer patterns; and
polishing the upper insulating layer to expose upper surfaces of the lower electrodes.

10. The method of claim 9 , wherein the upper insulating layer is formed to include a material having a polishing selectivity with respect to the etch stop layer.

11. The method of claim 1 , further comprising forming protection layer patterns on sidewalls of the openings.

12. A method of manufacturing an MRAM device, the method comprising:
forming a mold structure on a substrate, the mold structure including a first sacrificial layer, an etch stop layer, and a second sacrificial layer sequentially stacked on the substrate, with openings arranged through the first sacrificial layer, the etch stop layer, and the second sacrificial layer;
forming lower electrodes filling the openings;
removing the first and second sacrificial layers and forming etch stop layer patterns on upper portions of sidewalls of the lower electrodes;
forming an upper insulating layer to fill a space between the etch stop layer patterns, wherein the upper insulating layer partially defines an air pad arranged between adjacent ones of the lower electrodes;
polishing the upper insulating layer and the lower electrodes until the etch stop layer patterns are exposed to form an upper insulating layer pattern between the etch stop layer patterns;
forming a first magnetic layer, a tunnel barrier layer, a second magnetic layer, and an upper electrode layer on the lower electrodes, the etch stop layer patterns, and the upper insulating layer pattern; and
etching portions of the upper electrode layer, the second magnetic layer, the tunnel barrier layer, the first magnetic layer, the upper insulating layer pattern, and the etch stop layer patterns to form a plurality of magnetic tunnel junction (MTJ) structures, wherein each MTJ structure includes a sequentially stacked first magnetic layer pattern, tunnel layer pattern, and second magnetic layer pattern, each MTJ structure further contacting a corresponding one of the lower electrodes.

13. The method of claim 12 , wherein forming the etch stop layer patterns includes:
removing the first sacrificial layer to expose the etch stop layer; and
removing the second sacrificial layer and portions of the etch stop layer to form the etch stop layer patterns, said etch stop layer patterns surrounding upper portions of sidewalls of the lower electrodes.

14. The method of claim 13 , wherein removing portions of the etch stop layer includes:
forming capping spacers on sidewalls of the lower electrodes to protrude from the etch stop layer; and
etching portions of the etch stop layer between the capping spacers.

15. The method of claim 12 , wherein the etch stop layer is formed to include silicon nitride, and wherein the upper insulating layer is formed to include silicon oxide.

16. A method of manufacturing an MRAM device, the method comprising:
forming a plurality of lower electrodes on a substrate;
forming etch stop layer patterns surrounding an upper portion of a sidewall of each of the lower electrodes, wherein forming the etch stop layer patterns includes: forming capping spacers comprising an insulating material on sidewalls of the lower electrodes, said capping spacers protruding from the etch stop layer; and etching portions of the etch stop layer between the capping spacers;
forming an upper insulating layer pattern between the etch stop layer patterns to cover an air pad arranged between the lower electrodes; and
forming a plurality of magnetic tunnel junction (MTJ) structures, each comprising a first magnetic layer pattern, a tunnel layer pattern, and a second magnetic layer pattern, wherein each MTJ structure contacts a respective one of the lower electrodes.

17. The method of claim 16 , further comprising:
sequentially forming a first sacrificial layer, an etch stop layer, and a second sacrificial layer on a substrate;
partially etching the second sacrificial layer, the etch stop layer, and the first sacrificial layer to form openings therethrough; and
forming a lower electrode in each of the openings.

18. The me

Assignees

• Noh Eun-Sun
• Park Jong-Chul
• Kwon Shin
• Kwon Hyung-Joon
• Kim Chae-Lyoung
• Yoon Hye-Ji
• Samsung Electronics Co Ltd

Inventors

• Noh Eun-Sun
• Park Jong-Chul
• Kwon Shin
• Kwon Hyung-Joon
• Kim Chae-Lyoung
• Yoon Hye-Ji

Classifications

• H01L27/222

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H01L43/12 Primary

  Electricity · mapped topic

• H10N50/01 Primary

  Manufacture or treatment · CPC title