Ultrasonic transducers in complementary metal oxide semiconductor (CMOS) wafers and related apparatus and methods

Patent metadata

Field	Value
Publication number	US-10177139-B2
Application number	US-201815865774-A
Country	US
Kind code	B2
Filing date	Jan 9, 2018
Priority date	Apr 18, 2014
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices. A metallization layer of a CMOS wafer may be removed by sacrificial release to create a cavity of an ultrasonic transducer. Remaining layers may form a membrane of the ultrasonic transducer.

First claim

What is claimed is:

1. An ultrasound device, comprising:
an integrated circuit having a transistor gate layer formed over a substrate;
a plurality of metallization layers disposed above the transistor gate layer; and
an ultrasonic transducer formed in the plurality of metallization layers above the transistor gate layer, the ultrasonic transducer further comprising:
a bottom electrode formed above a first of the plurality of metallization layers;
a cavity disposed above the bottom electrode, the cavity representing a partial void of a second of the plurality of metallization layers; and
a top electrode disposed above the cavity and formed below a third of the plurality of metallization layers.

2. The ultrasound device of claim 1 , wherein the bottom electrode and the top electrode comprise liner layers of the second of the plurality of metallization layers.

3. The ultrasound device of claim 1 , wherein the bottom electrode comprises a first plurality of vias disposed between the first of the plurality of metallization layers and the cavity, and the top electrode comprises a second plurality of vias disposed between the cavity and the third of the plurality of metallization layers.

4. The ultrasound device of claim 1 , further comprising a fourth and a fifth of the plurality of metallization layers, disposed between the first of the plurality of metallization layers and the transistor gate layer.

5. The ultrasound device of claim 1 , wherein the integrated circuit is disposed directly beneath the ultrasonic transducer.

6. The ultrasound device of claim 1 , wherein the third of the plurality of metallization layers is a topmost metallization layer, and the second of the plurality of metallization layers is disposed immediately beneath the third of the plurality of metallization layers.

7. The ultrasound device of claim 1 , wherein the ultrasonic transducer further comprises an acoustic membrane that includes the top electrode and the third of the plurality of metallization layers.

8. The ultrasound device of claim 7 , wherein the acoustic membrane further comprises:
a first dielectric layer in which the third of the plurality of metallization layers is disposed; and
a second dielectric layer in which the second of the plurality of metallization layers is disposed.

9. The ultrasound device of claim 8 , wherein the acoustic membrane further comprises a plurality of vias that electrically connect the top electrode and the third of the plurality of metallization layers.

10. The ultrasound device of claim 7 , wherein the acoustic membrane further comprises:
a first passivation layer disposed over the third of the plurality of metallization layers; and
a second passivation layer disposed over the first passivation layer, the second passivation layer also sealing access holes used to create the cavity.

Assignees

• Butterfly Network Inc

Inventors

• Rothberg Jonathan M
• Fife Keith G
• Sanchez Nevada J
• Alie Susan A

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title