High accuracy clock synchronization circuit

Patent metadata

Field	Value
Publication number	US-10171094-B2
Application number	US-201715492573-A
Country	US
Kind code	B2
Filing date	Apr 20, 2017
Priority date	Apr 25, 2016
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A circuit device includes a phase comparator that performs phase comparison between an input signal based on an oscillation signal and a reference signal, a processor that performs a signal process on frequency control data based on a result of the phase comparison, and an oscillation signal generation circuit that generates the oscillation signal having an oscillation frequency which is set on the basis of frequency control data having undergone the signal process. The phase comparator includes a counter that performs a count operation by using the input signal, and performs the phase comparison by comparing a count value in the counter inn (where n is an integer of 2 or more) cycles of the reference signal with an expected value of the count value in integers.

First claim

What is claimed is:

1. A circuit device comprising:
a comparator that performs a comparison between an input signal based on an oscillation signal and a reference signal, the comparator including a counter that performs a count operation by using the input signal, and performs the comparison by comparing a count value in the counter in n (where n is an integer of 2 or more) cycles of the reference signal with an expected value of the count value in integers;
a processor that performs a signal process on frequency control data based on a result of the comparison; and
an oscillation signal generation circuit that generates the oscillation signal having an oscillation frequency which is set on the basis of the frequency control data having undergone the signal process.

2. The circuit device according to claim 1 ,
wherein n is set to k1 (where k1 is an integer of 2 or more) in at least a state in which the oscillation frequency is set based on a frequency of the reference signal.

3. The circuit device according to claim 2 ,
wherein n is set to k2 (where k2 is an integer of 1 or more and below k1) at the time of starting to set the oscillation frequency based on the frequency of the reference signal.

4. An oscillator comprising:
the circuit device according to claim 3 ; and
a resonator that is used to generate the oscillation signal.

5. The circuit device according to claim 2 ,
wherein n is set to k3 (where k3 is an integer of 1 or more and below k1) in a test mode.

6. The circuit device according to claim 2 ,
wherein, in a case where n is set to k4 (where k4 is an integer of 1 or more and below k1), the comparator sets n to k5 (where k5 is an integer of 2 or more and k1 or less) more than k4 if a difference between the count value and the expected value is equal to or less than a predetermined value.

7. An oscillator comprising:
the circuit device according to claim 2 ; and
a resonator that is used to generate the oscillation signal.

8. The circuit device according to claim 1 ,
wherein n is set to be variable.

9. The circuit device according to claim 8 ,
wherein, in a case where n is set to k4 (where k4 is an integer of 1 or more), the comparator sets n to k5 (where k5 is an integer of 2 or more) more than k4 if a difference between the count value and the expected value is equal to or less than a predetermined value.

10. The circuit device according to claim 8 ,
wherein a gain adjustment coefficient for a result of the comparison is set depending on a value of n.

11. The circuit device according to claim 1 ,
wherein the comparator shifts bits of frequency setting data so as to obtain the expected value, and compares the obtained expected value with the count value.

12. The circuit device according to claim 11 ,
wherein the counter counts down by using the input signal in n cycles of the reference signal with the expected value as an initial value, and outputs the count value obtained through countdown as a result of the comparison.

13. The circuit device according to claim 1 ,
wherein the processor performs the signal process including at least one of a temperature compensation process, an aging correction process, and a process of correcting capacitance characteristics of a variable capacitance capacitor connected to a resonator used to generate the oscillation signal, and a digital filter process on error data which is the result of the comparison.

14. The circuit device according to claim 1 , further comprising:
a digital interface;
wherein the oscillation signal generation circuit:
generates the oscillation signal by using the frequency control data based on the result of the comparison in a first mode; and
generates the oscillation signal by using the frequency control data which is generated based on externally generated frequency control data which is input via the digital interface in a second mode.

15. An oscillator comprising:
the circuit device according to claim 1 ; and
a resonator that is used to generate the oscillation signal.

16. An electronic apparatus comprising the circuit device according to claim 1 .

17. A vehicle comprising the circuit device according to claim 1 .

18. A negative feedback control device comprising:
a comparator that performs a comparison between an input signal based on an oscillation signal and a reference signal to generate error data, the comparator including a counter that performs a count operation by using the input signal, and performs the comparison by comparing a count value in the counter in n (where n is an integer of 2 or more) cycles of the reference signal with an expected value of the count value in integers;
a processor that performs negative feedback control on the error data to generate frequency control data; and
an oscillation signal generation circuit that generates the oscillation signal having an oscillation frequency which is set on the basis of the frequency control data.

Assignees

• Seiko Epson Corp

Inventors

• Nakajima Katsuhito

Classifications

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/095 Primary

  using a lock detector (H03L7/087 takes precedence) · CPC title

• H03L7/181

  a numerical count result being used for locking the loop, the counter counting during fixed time intervals {(H03L7/1806 takes precedence)} · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L1/022

  by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature (H03L1/021 takes precedence) · CPC title